利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

20 条记录 (耗时 0.015 秒)

    ROW HAMMER REFRESH COMMAND
    2.
    发明申请
    ROW HAMMER REFRESH COMMAND 有权

    公开(公告)号：US20160225433A1

    公开(公告)日：2016-08-04

    申请号：US14955012

    申请日：2015-11-30

    申请人： Intel Corporation

    发明人： Kuljit S Bains ,  John B Halbert ,  Christopher P Mozak ,  Theodore Z Schoenborn ,  Zvika Greenfield

    IPC分类号： G11C11/406 ,  G11C11/4091

    CPC分类号： G11C11/4091 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/7211 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

    摘要： A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

    摘要翻译： 内存控制器发出目标刷新命令。 存储器件的特定行可以是重复访问的目标。 当行在时间阈值（也称为“锤击”或“行锤事件”）中被重复访问时，物理上相邻的行（“受害者”行）可能经历数据损坏。 存储器控制器接收行敲击事件的指示，识别与行锤事件相关联的行，并且将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

    Memory device error check and scrub mode and error transparency
    3.
    发明授权
    Memory device error check and scrub mode and error transparency 有权

    公开(公告)号：US10127101B2

    公开(公告)日：2018-11-13

    申请号：US14998184

    申请日：2015-12-26

    申请人： Intel Corporation

    发明人： John B Halbert ,  Kuljit S Bains

    IPC分类号： H03M13/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  H03M13/09 ,  G11C29/42 ,  G11C11/401

    摘要： An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

    FAST EXIT FROM DRAM SELF-REFRESH
    6.
    发明申请
    FAST EXIT FROM DRAM SELF-REFRESH 有权
    快速退出DRAM自我修复

    公开(公告)号：US20160196866A1

    公开(公告)日：2016-07-07

    申请号：US15068925

    申请日：2016-03-14

    申请人： INTEL CORPORATION

    发明人： Kuljit S Bains

    IPC分类号： G11C11/406

    CPC分类号： G11C11/40615 ,  G06F12/02 ,  G06F13/1636 ,  G11C2211/4067

    摘要： Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.

    摘要翻译： 本发明的实施例描述了一种动态随机存取存储器（DRAM）装置，其可以中止自刷新模式以改善从自动刷新的DRAM低功率状态的退出时间。 在执行自刷新模式期间，DRAM设备可以从可操作地耦合到DRAM设备的存储器控​​制器接收信号（例如，器件使能信号）。 响应于接收到来自存储器控制器的信号，DRAM设备可以中止自刷新模式。

    INTERNAL CONSECUTIVE ROW ACCESS FOR LONG BURST LENGTH
    10.
    发明申请
    INTERNAL CONSECUTIVE ROW ACCESS FOR LONG BURST LENGTH 审中-公开
    内部协调一致的长期接触

    公开(公告)号：US20160378366A1

    公开(公告)日：2016-12-29

    申请号：US14749605

    申请日：2015-06-24

    申请人： Intel Corporation

    发明人： Shigeki Tomishima ,  Shih-Lien L. Lu ,  Kuljit S Bains

    IPC分类号： G06F3/06 ,  G11C15/00 ,  G11C7/10

    CPC分类号： G11C7/1072 ,  G11C7/08 ,  G11C7/1018 ,  G11C7/1021 ,  G11C7/1045 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/409

    摘要： A memory device executes internal operations to provide a programmable burst length. The memory device includes multiple banks that are independent and separately addressable. The memory device selects a number of banks to operate in burst sequence, where all selected banks operate on a command sent from an associated memory controller. In response to receiving the access command, the memory device generates multiple internal operations to cause all selected memory banks to execute the access command, without requiring multiple commands from the memory controller.

    摘要翻译： 存储器件执行内部操作以提供可编程突发长度。 存储器件包括独立且可单独寻址的多个存储体。 存储器设备选择多个存储体以突发序列操作，其中所有选择的存储体根据从相关联的存储器控​​制器发送的命令进行操作。 响应于接收到访问命令，存储器设备生成多个内部操作以使得所有选择的存储体执行访问命令，而不需要来自存储器控制器的多个命令。