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    Combining Materials in Different Components of Selector Elements of Integrated Circuits
    1.
    发明申请
    Combining Materials in Different Components of Selector Elements of Integrated Circuits 审中-公开
    将材料组合在集成电路选择元件的不同组件中

    公开(公告)号：US20170062522A1

    公开(公告)日：2017-03-02

    申请号：US15235992

    申请日：2016-08-12

    Applicant: Intermolecular, Inc.

    Inventor： Salil Mujumdar ,  Abhijit Pethe ,  Ashish Bodke ,  Kevin Kashefi

    IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

    CPC classification number: H01L27/24 ,  G11C11/1659 ,  G11C13/003 ,  G11C2213/15 ,  G11C2213/52 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/148

    Abstract: Provided are selector elements having snapback characteristics and non-volatile memory cells comprising such selector elements. To achieve its snapback characteristic, a selector element may include a dielectric layer comprising an alloy of two or more materials. In the same or other embodiments, the selector element may include a doped electrode, such carbon electrodes doped with silicon, germanium, and/or selenium. Concentrations of different materials forming an alloy may vary throughout the thickness of the dielectric layer. For example, the concentration of the first one alloy material may be higher in the center of the dielectric layer than near the interfaces of the dielectric layer with the electrodes. Some examples of this alloy material include germanium, indium, and aluminum. Examples of other materials in the same alloy include silicon, gallium, arsenic, and antimony. In some embodiments, the alloy is formed by three or more elements, such as indium gallium arsenic.

    Abstract translation: 提供具有快速恢复特性的选择器元件和包括这种选择器元件的非易失性存储单元。 为了实现其回跳特性，选择器元件可以包括包含两种或更多种材料的合金的电介质层。 在相同或其它实施例中，选择器元件可以包括掺杂电极，掺杂有硅，锗和/或硒的碳电极。 形成合金的不同材料的浓度可以在电介质层的整个厚度上变化。 例如，第一种合金材料的浓度在电介质层的中心处可以比在具有电极的介电层的界面附近更高。 该合金材料的一些实例包括锗，铟和铝。 相同合金中的其它材料的实例包括硅，镓，砷和锑。 在一些实施例中，合金由三种或更多种元素形成，例如铟镓砷。

    Atomic Layer Deposition of HfAlC as a Metal Gate Workfunction Material in MOS Devices
    2.
    发明申请
    Atomic Layer Deposition of HfAlC as a Metal Gate Workfunction Material in MOS Devices 有权
    HfAlC作为MOS器件中金属栅极功能材料的原子层沉积

    公开(公告)号：US20160035631A1

    公开(公告)日：2016-02-04

    申请号：US14094691

    申请日：2013-12-02

    Applicant: GLOBALFOUNDRIES, INC. ,  INTERMOLECULAR INC.

    Inventor： Albert Sanghyup Lee ,  Paul Besser ,  Kisik Choi ,  Edward L Haywood ,  Hoon Kim ,  Salil Mujumdar

    IPC: H01L21/66 ,  H01L21/28

    CPC classification number: H01L22/10 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28194 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/94

    Abstract: ALD of HfxAlyCz films using hafnium chloride (HfCl4) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfCl4 pulse time allows for control of the Al % incorporation in the HfxAlyCz film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfxAlyCz work function layer coupled with ALD deposited HfO2 high-k gate dielectric layers was quantified to be mid-gap at ˜4.6 eV. Thus, HfxAlyCz is a promising metal gate work function material allowing for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit (IC) devices.

    Abstract translation: 使用氯化铪（HfCl4）和三甲基铝（TMA）前体的HfxAlyCz膜的ALD可与后沉积退火工艺和ALD衬垫组合以控制高k金属栅极器件中的器件特性。 HfCl 4脉冲时间的变化允许控制HfxAlyCz膜中的Al％掺入在10-13％的范围内。 组合工艺工具可用于各种材料堆的快速电气和材料表征。 金属氧化物半导体电容器（MOSCAP）器件中具有HfxAlyCz功函数层与ALD沉积HfO 2高k栅极电介质层耦合的有效功函数（EWF）被定义为〜4.6eV的中间间隙。 因此，HfxAlyCz是有希望的金属栅极功能材料，允许调谐预期的多Vth集成电路（IC）器件的器件阈值电压（Vth）。

    Two Step Deposition of High-k Gate Dielectric Materials
    3.
    发明申请
    Two Step Deposition of High-k Gate Dielectric Materials 审中-公开
    高k栅介质材料的两步沉积

    公开(公告)号：US20150140838A1

    公开(公告)日：2015-05-21

    申请号：US14083761

    申请日：2013-11-19

    Applicant: Intermolecular Inc.

    Inventor： Kevin Kashefi ,  Amol Joshi ,  Salil Mujumdar

    IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28

    CPC classification number: H01L29/517 ,  C23C16/405 ,  C23C16/45527 ,  C23C16/56 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02318 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6659

    Abstract: Methods and apparatus for forming a dielectric layer for use as a gate dielectric are provided. A high-k layer is formed with first ALD process using a halogen-based precursor. The metal in the halogen-based precursor may be at least one of hafnium, zirconium, or titanium. The halogen in the halogen-based precursor may be at least one of fluorine, chlorine, or iodine. In some embodiments, the halogen-based metal precursor includes hafnium chloride. The remainder of the high-k layer is formed with second ALD process using a metal organic-based precursor. The metal in the metal organic-based precursor may be at least one of hafnium, zirconium, or titanium. The organic ligands in the metal organic-based precursor may be at least one of β-diketonate precursors, alkoxide precursors, amino precursors. In some embodiments, the metal organic-based precursor includes amino precursors.

    Abstract translation: 提供了形成用作栅极电介质的电介质层的方法和装置。 使用卤素前体的第一ALD工艺形成高k层。 卤素前体中的金属可以是铪，锆或钛中的至少一种。 卤素前体中的卤素可以是氟，氯或碘中的至少一种。 在一些实施方案中，卤素基金属前体包括氯化铪。 高k层的其余部分由使用金属有机基前体的第二ALD工艺形成。 金属有机基前体中的金属可以是铪，锆或钛中的至少一种。 金属有机基前体中的有机配体可以是β-二酮前体，醇盐前体，氨基前体中的至少一种。 在一些实施方案中，金属有机基前体包括氨基前体。

    TRANSITION METAL ALUMINATE AND HIGH K DIELECTRIC SEMICONDUCTOR STACK
    8.
    发明申请
    TRANSITION METAL ALUMINATE AND HIGH K DIELECTRIC SEMICONDUCTOR STACK 审中-公开
    过渡金属铝和高K介电半导体堆叠

    公开(公告)号：US20140175618A1

    公开(公告)日：2014-06-26

    申请号：US13723853

    申请日：2012-12-21

    Applicant: Intermolecular Inc.

    Inventor： Salil Mujumdar

    IPC: H01L21/02

    CPC classification number: H01L21/02178 ,  H01L21/02175 ,  H01L21/02181

    Abstract: Methods of forming a high K dielectric semiconductor stack are described. A semiconductor substrate is provided, in which the native oxide layer is removed. A transition metal aluminate layer is deposited onto the semiconductor substrate across discrete multiple regions in a combinatorial manner. A high K dielectric layer is deposited onto the transition metal aluminate layer across the discrete multiple regions in a combinatorial manner. The transition metal aluminate layer and the high K dielectric layer are patterned to form a plurality of high K dielectric semiconductor stacks across discrete multiple regions. A three-five semiconductor substrate or a germanium substrate can be used in methods of forming a high K dielectric semiconductor stack.

    Abstract translation: 描述形成高K电介质半导体堆叠的方法。 提供半导体衬底，其中去除了自然氧化物层。 过渡金属铝酸盐层以组合的方式跨越离散的多个区域沉积到半导体衬底上。 高K电介质层以组合的方式跨越离散的多个区域沉积到过渡金属铝酸盐层上。 将过渡金属铝酸盐层和高K电介质层图案化以在离散的多个区域上形成多个高K电介质半导体堆叠。 在形成高K电介质半导体堆叠的方法中可以使用三分之一半导体衬底或锗衬底。

    Sacrificial Low Work Function Cap Layer
    9.
    发明申请
    Sacrificial Low Work Function Cap Layer 审中-公开
    牺牲低功能帽层

    公开(公告)号：US20140099785A1

    公开(公告)日：2014-04-10

    申请号：US13645259

    申请日：2012-10-04

    Applicant: INTERMOLECULAR, INC.

    Inventor： Salil Mujumdar ,  Amol Joshi

    IPC: H01L21/02

    CPC classification number: H01L21/02697 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: A method includes forming an interlayer on a substrate, depositing a dielectric on the interlayer to form a dielectric stack, forming a sacrificial cap layer over the dielectric stack, processing the substrate to alter properties of the dielectric stack, and removing the sacrificial cap layer.

    Abstract translation: 一种方法包括在衬底上形成中间层，在中间层上沉积电介质以形成电介质叠层，在电介质叠层上形成牺牲覆盖层，处理衬底以改变电介质层的性质，以及去除牺牲覆盖层。

    Metal-insulator-semiconductor (MIS) contact with controlled defect density
    10.
    发明申请
    Metal-insulator-semiconductor (MIS) contact with controlled defect density 审中-公开
    金属 - 绝缘体 - 半导体（MIS）接触具有受控的缺陷密度

    公开(公告)号：US20150380309A1

    公开(公告)日：2015-12-31

    申请号：US14315718

    申请日：2014-06-26

    Applicant: Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

    Inventor： Salil Mujumdar ,  Amol Joshi ,  Kevin Kashefi ,  Albert Sanghyup Lee ,  Abhijit Pethe ,  Bin Yang

    IPC: H01L21/768 ,  H01L23/535

    CPC classification number: H01L29/517 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/02312 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/285 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Metal-insulator-semiconductor (MIS) contacts for germanium and its alloys include insulator layers of oxygen-deficient metal oxide deposited by atomic layer deposition (ALD). The oxygen deficiency reduces the tunnel barrier resistance of the insulator layer while maintaining the layer's ability to prevent Fermi-level pinning at the metal/semiconductor interface. The oxygen deficiency is controlled by optimizing one or more ALD parameters such as shortened oxidant pulses, use of less-reactive oxidants such as water, heating the substrate during deposition, TMA “cleaning” of native oxide before deposition, and annealing after deposition. Secondary factors include reduced process-chamber pressure, cooled oxidant, and shortened pulses of the metal precursor.

    Abstract translation: 用于锗及其合金的金属 - 绝缘体 - 半导体（MIS）触点包括通过原子层沉积（ALD）沉积的缺氧金属氧化物的绝缘体层。 缺氧会降低绝缘体层的隧道势垒阻力，同时保持层在金属/半导体界面处防止费米能级钉扎的能力。 通过优化一个或多个ALD参数，例如缩短的氧化剂脉冲，使用较少反应性的氧化剂例如水，在沉积期间加热衬底，在沉积之前对自然氧化物进行TMA“清洁”，以及沉积后的退火来优化一个或多个ALD参数来控制氧缺乏。 次要因素包括降低的处理室压力，冷却的氧化剂和金属前体的缩短的脉冲。

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