公开(公告)号：US20170077076A1

公开(公告)日：2017-03-16

申请号：US15360121

申请日：2016-11-23

Applicant: Invensas Corporation

Inventor： LIANG WANG ,  HONG SHEN ,  RAJESH KATKAR

IPC: H01L25/16 ,  H01L25/00 ,  H01L21/48 ,  H01L23/498 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/11 ,  H01L25/115 ,  H01L25/165 ,  H01L25/50 ,  H01L28/40 ,  H01L28/65 ,  H01L2224/05009 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1205 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/00

Abstract: A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

Abstract translation: 制造集成电路封装的方法包括提供具有限定空腔的第一区域的处理晶片。 在第一区域形成电容器。 电容器具有一对电极，每对电极耦合到一对导电焊盘中的一个，其至少一个设置在处理晶片的下表面上。 还提供了具有上表面的插入件，其具有导电焊盘和设置在其上的至少一个半导体管芯。 芯片具有与内插器的再分配层（RDL）电导耦合的集成电路。 把手晶片的下表面被结合到插入件的上表面，使得模具设置在空腔的下方或内部，并且处理晶片的导电焊盘以金属间隔结合到插入件的导电焊盘上， 金属键。

公开(公告)号：US20160049361A1

公开(公告)日：2016-02-18

申请号：US14833979

申请日：2015-08-24

Applicant: INVENSAS CORPORATION

Inventor： LIANG WANG ,  HONG SHEN ,  RAJESH KATKAR

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L28/60 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/11 ,  H01L25/115 ,  H01L25/165 ,  H01L25/50 ,  H01L28/40 ,  H01L28/65 ,  H01L2224/05009 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1205 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/00

Abstract: A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

公开(公告)号：US20170053886A1

公开(公告)日：2017-02-23

申请号：US14832996

申请日：2015-08-21

Applicant: INVENSAS CORPORATION

Inventor： CYPRIAN EMEKA UZOH ,  RAJESH KATKAR

IPC: H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/17 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/034 ,  H01L2224/03612 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1012 ,  H01L2224/10155 ,  H01L2224/11003 ,  H01L2224/11013 ,  H01L2224/111 ,  H01L2224/1111 ,  H01L2224/1112 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/11438 ,  H01L2224/1144 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/1161 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11912 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13187 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/381 ,  H05K3/3436 ,  H05K3/3478 ,  H05K2203/0415 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

Abstract translation: 设备和技术的代表性实现提供用于使用高和/或细间距物理连接来耦合各种载体，印刷电路板（PCB）部件，集成电路（IC）芯片等的互连结构和部件。 布置多层导电结构或材料以形成互连结构和部件。 不可润湿的屏障可以与一个或多个层一起使用以形成包括一个或多个层的间距的形状。