公开(公告)号：US20150043169A1

公开(公告)日：2015-02-12

申请号：US13964263

申请日：2013-08-12

Applicant: Infineon Technologies AG

Inventor： Frank WINTER ,  Ottmar GEITNER ,  Ivan NIKITIN ,  Juergen HOEGERL

IPC: H05K1/18

CPC classification number: H01L23/4334 ,  H01L21/4871 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/8384 ,  H05K1/185 ,  H05K3/4608 ,  Y10T29/49002

Abstract: According to an exemplary aspect an electronic module is provided, wherein the electronic module comprises an electronic chip comprising at least one electronic component, a spacing element comprising a main surface arranged on the electronic chip and being in thermally conductive connection with the at least one electronic component, and a mold compound at least partially enclosing the electronic chip and the spacing element, wherein the spacing element comprises a lateral surface which is in contact to the mould compound and comprises surface structures.

Abstract translation: 根据示例性方面，提供一种电子模块，其中所述电子模块包括电子芯片，该电子芯片包括至少一个电子元件，间隔元件，包括布置在所述电子芯片上并与所述至少一个电子元件导热连接的主表面 以及至少部分地包围电子芯片和间隔元件的模具化合物，其中间隔元件包括与模具化合物接触并包括表面结构的侧表面。

公开(公告)号：US20150325535A1

公开(公告)日：2015-11-12

申请号：US14272535

申请日：2014-05-08

Applicant: Infineon Technologies AG

Inventor： Stephan HENNECK ,  Evelyn NAPETSCHNIG ,  Daniel PEDONE ,  Bernhard WEIDGANS ,  Simon FAISS ,  Ivan NIKITIN

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/03424 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03472 ,  H01L2224/03614 ,  H01L2224/05007 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05583 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2924/01023

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.

Abstract translation: 根据各种实施例的用于处理半导体器件的方法可以包括：在半导体工件上沉积第一金属化层; 图案化第一金属化层; 以及在图案化的第一金属化层上沉积第二金属化层，其中沉积第二金属化层包括无电沉积工艺，包括将图案化的第一金属化层浸入金属电解质中。

公开(公告)号：US20170092563A1

公开(公告)日：2017-03-30

申请号：US15375855

申请日：2016-12-12

Applicant: Infineon Technologies AG

Inventor： Frank WINTER ,  Ottmar GEITNER ,  Ivan NIKITIN ,  Jürgen HÖGERL

IPC: H01L23/433 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/4334 ,  H01L21/4871 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/8384 ,  H05K1/185 ,  H05K3/4608 ,  Y10T29/49002

Abstract: According to an exemplary aspect an electronic module is provided, wherein the electronic module comprises an electronic chip comprising at least one electronic component, a spacing element comprising a main surface arranged on the electronic chip and being in thermally conductive connection with the at least one electronic component, and a mold compound at least partially enclosing the electronic chip and the spacing element, wherein the spacing element comprises a lateral surface which is in contact to the mould compound and comprises surface structures.

公开(公告)号：US20150131247A1

公开(公告)日：2015-05-14

申请号：US14076976

申请日：2013-11-11

Applicant: Infineon Technologies AG

Inventor： Ivan NIKITIN ,  Petteri PALM ,  Joachim MAHLER

IPC: H05K3/32 ,  H05K1/18

CPC classification number: H01L24/97 ,  H01L24/24 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A method which comprises arranging a plurality of electronic chips in a plurality of chip accommodation cavities each defined by a respective surface portion of a substrate and a wall delimited by a respective one of a plurality of holes in an electrically conductive frame arranged on the substrate, at least partially encapsulating the electronic chips in the chip accommodation cavities by an encapsulant, and forming electrically conductive contacts for electrically contacting the at least partially encapsulated electronic chips.

Abstract translation: 一种方法，其包括将多个电子芯片布置在由芯片的相应表面部分限定的多个芯片容置空腔中，以及由布置在基板上的导电框架中的多个孔中的相应一个孔限定的壁， 至少部分地通过密封剂将所述电子芯片封装在所述芯片容纳腔中，以及形成用于电接触所述至少部分封装的电子芯片的导电触点。

公开(公告)号：US20150035170A1

公开(公告)日：2015-02-05

申请号：US13959712

申请日：2013-08-05

Applicant: Infineon Technologies AG

Inventor： Ivan NIKITIN ,  Joachim MAHLER ,  Khalil HOSSEINI

IPC: H01L25/07 ,  H01L23/367

CPC classification number: H01L25/074 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49827 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/08168 ,  H01L2224/32225 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/40101 ,  H01L2224/40137 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/456 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076

Abstract: A device includes a substrate including an electrically insulating core, a first electrically conductive material arranged over a first main surface of the substrate, and a second electrically conductive material arranged over a second main surface of the substrate opposite to the first main surface. The device further includes an electrically conductive connection extending from the first main surface to the second main surface and electrically coupling the first electrically conductive material and the second electrically conductive material, a first semiconductor chip arranged over the first main surface and electrically coupled to the first electrically conductive material, and a second semiconductor chip arranged over the second main surface and electrically coupled to the second electrically conductive material.

Abstract translation: 一种器件包括：衬底，其包括电绝缘芯，布置在衬底的第一主表面上的第一导电材料和布置在与第一主表面相对的衬底的第二主表面上的第二导电材料。 该装置还包括从第一主表面延伸到第二主表面并且电耦合第一导电材料和第二导电材料的导电连接，第一半导体芯片，布置在第一主表面上并电耦合到第一导电材料 导电材料和布置在第二主表面上并电耦合到第二导电材料的第二半导体芯片。

公开(公告)号：US20180102302A1

公开(公告)日：2018-04-12

申请号：US15730758

申请日：2017-10-12

Applicant: Infineon Technologies AG

Inventor： Andreas GRASSMANN ,  Wolfram HABLE ,  Juergen HOEGERL ,  Angela KESSLER ,  Ivan NIKITIN ,  Achim STRASS

IPC: H01L23/373 ,  H01L23/492 ,  H01L23/66 ,  H01L23/00

CPC classification number: H01L23/3735 ,  H01L23/4334 ,  H01L23/4924 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45014 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/206

Abstract: A chip carrier which comprises a thermally conductive and electrically insulating sheet, a first electrically conductive structure on a first main surface of the sheet, and a second electrically conductive structure on a second main surface of the sheet, wherein the first electrically conductive structure and the second electrically conductive structure extend beyond a lateral edge of the sheet.

公开(公告)号：US20180082925A1

公开(公告)日：2018-03-22

申请号：US15710852

申请日：2017-09-21

Applicant: Infineon Technologies AG

Inventor： Andreas GRASSMANN ,  Wolfram HABLE ,  Juergen HOEGERL ,  Ivan NIKITIN ,  Achim STRASS

IPC: H01L23/42 ,  H01L23/473

CPC classification number: H01L23/42 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/473 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/552 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A package which comprises at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and a shielding layer on at least part of an external surface of the encapsulant configured for shielding an interior of the package with regard to cooling fluid for removing thermal energy from the at least one electronic chip.

公开(公告)号：US20180082921A1

公开(公告)日：2018-03-22

申请号：US15709493

申请日：2017-09-20

Applicant: Infineon Technologies AG ,  HYUNDAI Motor Company ,  Kia Motor Corporation

Inventor： Andreas GRASSMANN ,  Juergen HOEGERL ,  Kiyoung JANG ,  Ivan NIKITIN

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/373 ,  H01L23/495 ,  H01L21/56 ,  H01L21/48

Abstract: A package comprising at least one electronic chip, a first heat removal body thermally coupled to a first main surface of the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and part of the first heat removal body, wherein at least part of a surface of the first heat removal body is roughened.