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    Method for the programming of the memory cells of a memory and a circuit to implement this method
    1.
    发明授权
    Method for the programming of the memory cells of a memory and a circuit to implement this method 失效
    用于存储器的存储器单元的编程和实现该方法的电路的方法

    公开(公告)号：US5022001A

    公开(公告)日：1991-06-04

    申请号：US258801

    申请日：1988-10-17

    申请人： Jacek Kowalski ,  Christophe Chevalier

    发明人： Jacek Kowalski ,  Christophe Chevalier

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/10 ,  G11C16/24

    CPC分类号： G11C16/10 ,  G11C16/24

    摘要： The use of charge pumps to supply bit lines, when programming memory cells connected to a bit line, is avoided by pre-charging this bit line simultaneously with the neutralization of the selection of this bit line. Subsequently, the pre-charging potential is uncoupled and the effects of the neutralization are stopped. It is known that this method of action prevents the breakdown of a single programming potential generator, used to supply all the bit lines. This results in a gain in space in the lay-out of the control circuits of the memory cells in the memory plane. This method can be implemented especially in page mode programming for memories where the memory cells have EEPROM-type floating-gate transistors.

    摘要翻译： 当编程连接到位线的存储器单元时，使用电荷泵来提供位线，可以通过对该位线的选择进行中和来同时对该位线进行预充电来避免。 随后，预充电电势解耦，中和的效果停止。 已知这种作用方法防止用于提供所有位线的单个编程电位发生器的击穿。 这导致在存储器平面中的存储器单元的控制电路的布局中的空间增益。 该方法尤其适用于存储器单元具有EEPROM型浮栅晶体管的存储器的页模式编程。

    Method and system for imposing print data
    2.
    发明授权
    Method and system for imposing print data 有权
    打印数据的方法和系统

    公开(公告)号：US07333246B1

    公开(公告)日：2008-02-19

    申请号：US10019853

    申请日：2000-05-05

    申请人： Jacek Kowalski ,  Petra Wegele

    发明人： Jacek Kowalski ,  Petra Wegele

    IPC分类号： H04N1/387 ,  H04N1/401 ,  G06F15/82 ,  G06F15/76 ,  G06K1/00 ,  B41J15/00 ,  B41J11/00 ,  B65H39/00 ,  B41L43/04

    CPC分类号： G06K15/00 ,  G03G2215/00936 ,  G06K2215/0062 ,  G06K2215/0082

    摘要： A method, system and computer program provides for making an image area correction in a printing system. Print data is provided in a logical page order corresponding to at least one signature for printing. At least one parameter of a recording medium on which the print data are printed is determined, this parameter being relevant to the position of the printing format on the recording medium, which is folded according to the signature. The position of the pages is then corrected according to this parameter prior to printing, in such a way that the print formats of successive pages of the finished signature are positioned accurately.

    摘要翻译： 方法，系统和计算机程序提供在打印系统中进行图像区域校正。 以与用于打印的至少一个签名相对应的逻辑页面顺序提供打印数据。 确定打印数据被打印的记录介质的至少一个参数，该参数与根据签名折叠的记录介质上的打印格式的位置相关。 然后在打印之前根据该参数来校正页面的位置，使得完成的签名的连续页面的打印格式被准确地定位。

    MOS integrated circuit with adjustable threshold voltage
    4.
    发明授权
    MOS integrated circuit with adjustable threshold voltage 失效
    MOS集成电路具有可调阈值电压

    公开(公告)号：US5394359A

    公开(公告)日：1995-02-28

    申请号：US944811

    申请日：1992-09-14

    申请人： Jacek Kowalski

    发明人： Jacek Kowalski

    IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

    CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5692 ,  G11C16/10

    摘要： The MOS cell with adjustable threshold voltage is a cell of the type with a memory that is electrically-erasable and programmable by storage of charges by tunnel effect in a floating gate. To obtain a circuit with adjustable threshold voltage, the cell is first of all "programmed" at zero so that all the charges that may be stored are removed and then it is "erased", with its source grounded, its drain taken to the high potential and its control gate taken to the potential desired for the threshold voltage V.sub.T of the circuit. At the end of this phase, the threshold voltage is adjusted. This device can be applied notably to circuits requiring precise voltage references in MOS technology, namely circuits of the detector or analog-digital converter type.

    摘要翻译： 具有可调阈值电压的MOS单元是具有通过在浮动栅极中的隧道效应存储电荷而可电擦除和编程的存储器的类型的单元。 为了获得具有可调节阈值电压的电路，电池首先被“编程”为零，以便可以存储的所有电荷被去除，然后被“擦除”，其源极接地，其漏极被吸收到高电平 电位及其控制栅极达到电路的阈值电压VT所需的电位。 在该阶段结束时，调整阈值电压。 该器件可以应用于MOS技术中需要精确电压参考的电路，即检测器或模数转换器类型的电路。

    Safety decive for integrated circuit
    5.
    发明授权
    Safety decive for integrated circuit 失效
    集成电路安全装置

    公开(公告)号：US5191498A

    公开(公告)日：1993-03-02

    申请号：US467903

    申请日：1990-01-22

    申请人： Jacek Kowalski

    发明人： Jacek Kowalski

    IPC分类号： G06K19/073 ,  G06K19/10 ,  H01L27/092 ,  H01L27/105

    CPC分类号： G06K19/073 ,  G06K19/07363 ,  G06K19/07372 ,  H01L27/0921 ,  H01L27/105

    摘要： Phenomena of unwanted programming, caused by the substrate currents of an integrated circuit, are prevented by providing for a measurement of these currents and for a circuit invalidating the operation of the integrated circuit when the result of this measurement goes beyond a certain threshold. In a preferred way, the measurement of the substrate current is obtained by making a bipolar type transistor, the base region of which is formed precisely by this substrate, or by making a a field-effect type of transistor, the gate of which and one of the active regions of which are connected to the ground terminal of the circuit. But theses two connections are different. One of the connections is direct while the other is a connection subjected to the fluctuations in the potential of the substrate.

    摘要翻译： 通过提供这些电流的测量以及当该测量的结果超过某个阈值时使集成电路的操作无效的电路来防止由集成电路的衬底电流引起的不期望的编程的现象。 在优选的方式中，通过制作基极区域由该衬底精确地形成的双极型晶体管，或通过制作场效应晶体管，其栅极和 其有源区域连接到电路的接地端子。 但这两个连接是不同的。 其中一个连接是直接的，而另一个是受到基板电位波动的连接。

    Read circuit for memory
    6.
    发明授权
    Read circuit for memory 失效
    读存储器电路

    公开(公告)号：US4896298A

    公开(公告)日：1990-01-23

    申请号：US147902

    申请日：1988-01-25

    申请人： Jacek Kowalski

    发明人： Jacek Kowalski

    IPC分类号： G11C17/00 ,  G11C7/24 ,  G11C16/06 ,  G11C16/24 ,  G11C16/26

    CPC分类号： G11C16/24 ,  G11C16/26 ,  G11C7/24

    摘要： A read circuit is disclosed for logic circuit type integrated circuits comprising a memory consisting of a matrix of memory cells. The memory cells are each addressable by rows and columns selected by row and column decoders. The read circuit, which is connected to the memory cells by a line called a bit line, comprises a pre-loading circuit for the bit line and a detection circuit that detects the discharging or non-discharging of the bit line depending on whether the memory cell selected is in the state "0" or "1", and also comprises a means to memorize the state that is read. The circuit further comprises means which make it possible, in read mode, to discharge the bit line regardless of whether the memory cell is in the state "1" or "0" and means that delay the moment of discharge. The invention can be applied to EPROMs or similar memories.

    摘要翻译： 公开了一种用于逻辑电路型集成电路的读取电路，其包括由存储器单元矩阵组成的存储器。 存储单元可以由行和列解码器选择的行和列进行寻址。 通过称为位线的线路连接到存储单元的读取电路包括用于位线的预加载电路和检测电路，该电路根据存储器是否检测位线的放电或不放电 所选择的单元处于状态“0”或“1”，并且还包括用于存储读取的状态的装置。 该电路还包括使得在读取模式下可以放电位线的装置，而不管存储器单元是处于“1”还是“0”，并且意味着延迟放电时刻。 本发明可以应用于EPROM或类似的存储器。

    Microcircuit chip card with contact and contactless operating modes
    9.
    发明授权
    Microcircuit chip card with contact and contactless operating modes 有权
    微电路芯片卡具有触点和非接触式工作模式

    公开(公告)号：US6003777A

    公开(公告)日：1999-12-21

    申请号：US226553

    申请日：1999-01-07

    申请人： Jacek Kowalski

    发明人： Jacek Kowalski

    IPC分类号： G06K7/00 ,  G06K19/07 ,  H02J17/00 ,  G06K19/06

    CPC分类号： G06K19/07769 ,  G06K19/0701 ,  G06K19/0723 ,  G06K7/0008

    摘要： A microcircuit with two contact and non-contact operating modes, including communication device (2) specific for the non-contact operating mode, communication device (3) specific for the contact operating mode, electronic circuit (4) common to both operating modes, a coil (L) for receiving an AC voltage (Va) by induction, a rectifier circuit (Pd) for rectifying the AC voltage (Va) to give a first microcircuit power supply voltage (Vcc1), at least one power supply contact (p1) for receiving a second microcircuit power supply voltage (Vcc2) a distribution line (5) for distributing the first (Vcc1), or second (Vcc2) power supply voltages, a switch circuit (6, 13) between the power supply contact (P1) and the distribution line (5), and controller (7, 8) for controlling the switch circuit, which controller (7, 8) are arranged to sense the AC voltage (Va) across the terminals of the coil (L), and close the switch circuit (6, 13) when the second power supply voltage (Vcc2) is present on the power supply contact, or give priority to opening the switch circuit when the AC voltage (Va) is present across the terminals of the coil.

    摘要翻译： 具有两个接触和非接触操作模式的微电路，包括专用于非接触操作模式的通信设备（2），专用于接触操作模式的通信设备（3），两种操作模式通用的电子电路（4） 用于通过感应接收AC电压（Va）的线圈（L），用于整流所述AC电压（Va）以产生第一微电路电源电压（Vcc1）的整流器电路（Pd），至少一个电源触点（p1 ），用于接收用于分配所述第一（Vcc1）或第二（Vcc2）电源电压的分配线路（5）的第二微电路电源电压（Vcc2），所述电源触点（P1）之间的开关电路（6,13） ）和分配线（5）以及用于控制开关电路的控制器（7,8），该控制器（7,8）被布置成感测线圈（L）的端子上的交流电压（Va），以及 当p上存在第二电源电压（Vcc2）时，闭合开关电路（6,13） 或者当交流电压（Va）存在于线圈的端子时，优先打开开关电路。