Ionic additives for extreme low dielectric constant chemical formulations
    5.
    发明授权
    Ionic additives for extreme low dielectric constant chemical formulations 失效
    用于极低介电常数化学配方的离子添加剂

    公开(公告)号:US06896955B2

    公开(公告)日:2005-05-24

    申请号:US10219164

    申请日:2002-08-13

    摘要: A process for depositing porous silicon oxide-based films using a sol-gel approach utilizing a precursor solution formulation which includes a purified nonionic surfactant and an additive among other components, where the additive is either an ionic additive or an amine additive which forms an ionic ammonium type salt in the acidic precursor solution. Using this precursor solution formulation enables formation of a film having a dielectric constant less than 2.5, appropriate mechanical properties, and minimal levels of alkali metal impurities. In one embodiment, this is achieved by purifying the surfactant and adding ionic or amine additives such as tetraalkylammonium salts and amines to the stock precursor solution. In some embodiments, the ionic additive is a compound chosen from a group of cationic additives of the general composition [NR(CH3)3]+A−, where R is a hydrophobic ligand of chain length 1 to 24, including tetramethylammonium and cetyltrimethylammonium, and A− is an anion, which may be chosen from the group consisting essentially of formate, nitrate, oxalate, acetate, phosphate, carbonate, and hydroxide and combinations thereof. Tetramethylammonium salts, or more generally tetraalkylammonium salts, or tetraorganoammonium salts or organoamines in acidic media are added to surfactant templated porous oxide precursor formulations to increase the ionic content, replacing alkali ion impurities (sodium and potassium) removed during surfactant purification, but which are found to exhibit beneficial effects in promoting the formation of the resulting dielectric.

    摘要翻译: 一种使用溶胶 - 凝胶方法沉积多孔氧化硅基膜的方法,该方法使用前体溶液制剂,其包含纯化的非离子表面活性剂和其它组分中的添加剂,其中添加剂是形成离子的离子添加剂或胺添加剂 铵型盐在酸性前体溶液中。 使用这种前体溶液制剂可以形成介电常数小于2.5,适当的机械性能和最低水平的碱金属杂质的薄膜。 在一个实施方案中,这通过纯化表面活性剂并将离子或胺添加剂例如四烷基铵盐和胺添加到原料前体溶液中来实现。 在一些实施方案中,离子添加剂是选自一般组成的阳离子添加剂组合物[NR(CH 3)3) 其中R是链长1至24的疏水性配体,包括四甲基铵和十六烷基三甲基铵,并且A是一种阴离子,其可以选自下组: 基本上由甲酸盐,硝酸盐,草酸盐,乙酸盐,磷酸盐,碳酸盐和氢氧化物组成。 在表面活性剂模板化的多孔氧化物前体制剂中加入四甲基铵盐或更一般的四烷基铵盐或四官能铵盐或有机胺,以增加离子含量,代替在表面活性剂纯化过程中除去的碱离子杂质(钠和钾),但发现 以促进所形成的电介质的形成。

    Method of forming a dual damascene structure using an amorphous silicon hard mask
    7.
    发明授权
    Method of forming a dual damascene structure using an amorphous silicon hard mask 失效
    使用非晶硅硬掩模形成双镶嵌结构的方法

    公开(公告)号:US06806203B2

    公开(公告)日:2004-10-19

    申请号:US10101540

    申请日:2002-03-18

    IPC分类号: H01L21302

    摘要: A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer and depositing a second hard mask layer on the first hard mask layer, where the second hard mask layer is an amorphous silicon layer. Afterwards, formation of the dual damascene structure is completed by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material.

    摘要翻译: 在其上已经形成有电介质层的基板上形成双镶嵌结构的方法。 在一个实施例中,该方法包括在电介质层上沉积第一硬掩模层并在第一硬掩模层上沉积第二硬掩模层,其中第二硬掩模层是非晶硅层。 然后,通过在电介质层中蚀刻金属布线图案和通孔图案并用导电材料填充蚀刻的金属布线图案和通孔图案来完成双镶嵌结构的形成。

    METHODS AND SYSTEMS FOR CONTROLLING CRITICAL DIMENSIONS IN TRACK LITHOGRAPHY TOOLS
    9.
    发明申请
    METHODS AND SYSTEMS FOR CONTROLLING CRITICAL DIMENSIONS IN TRACK LITHOGRAPHY TOOLS 有权
    用于控制轨迹切削工具中关键尺寸的方法和系统

    公开(公告)号:US20080032426A1

    公开(公告)日:2008-02-07

    申请号:US11834518

    申请日:2007-08-06

    IPC分类号: H01L21/66 B05C11/00

    CPC分类号: H01L22/20 H01L22/12

    摘要: A method of controlling wafer critical dimension (CD) uniformity on a track lithography tool includes obtaining a CD map for a wafer. The CD map includes a plurality of CD data points correlated with a multi-zone heater geometry map. The multi-zone heater includes a plurality of heater zones. The method also includes determining a CD value for a first heater zone of the plurality of heater zones based on one or more of the CD data points and computing a difference between the determined CD value for the first heater zone and a target CD value for the first heater zone. The method further includes determining a temperature variation for the first heater zone based, in part, on the computed difference and a temperature sensitivity of a photoresist deposited on the wafer and modifying a temperature of the first heater zone based, in part, on the temperature variation.

    摘要翻译: 控制轨道光刻工具上的晶片临界尺寸(CD)均匀性的方法包括获得晶片的CD图。 CD映射包括与多区加热器几何图相关的多个CD数据点。 多区加热器包括多个加热区。 该方法还包括基于CD数据点中的一个或多个来确定多个加热器区域中的第一加热器区域的CD值,并计算所确定的第一加热器区域的CD值与用于第一加热器区域的目标CD值之间的差值 第一加热区。 该方法还包括:部分地基于计算出的差异和沉积在晶片上的光致抗蚀剂的温度敏感度来确定第一加热器区域的温度变化,并且部分地基于温度改变第一加热器区域的温度 变异。

    METHOD OF FABRICATING AN ULTRA LOW-K DIELECTRIC SELF-ALIGNED VIA
    10.
    发明申请
    METHOD OF FABRICATING AN ULTRA LOW-K DIELECTRIC SELF-ALIGNED VIA 有权
    制造超低K电介质自对准方法

    公开(公告)号:US20140024220A1

    公开(公告)日:2014-01-23

    申请号:US13724698

    申请日:2012-12-21

    IPC分类号: H01L21/3065

    摘要: Methods of fabricating ultra low-k dielectric self-aligned vias are described. In an example, a method of forming a self-aligned via (SAV) in a low-k dielectric film includes forming a trench pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. A via pattern is formed in a masking layer formed above the metal nitride hardmask layer. The via pattern is etched at least partially into the low-k dielectric film, the etching comprising using a plasma etch using a chemistry based on CF4, H2, and a diluent inert gas composition.

    摘要翻译: 描述了制造超低k电介质自对准通孔的方法。 在一个示例中,在低k电介质膜中形成自对准通孔(SAV)的方法包括在形成在衬底上方的低k电介质膜上形成的金属氮化物硬掩模层中形成沟槽图案。 在形成在金属氮化物硬掩模层之上的掩模层中形成通孔图案。 通孔图案至少部分地被蚀刻到低k电介质膜中,蚀刻包括使用基于CF4,H2和稀释惰性气体组成的化学物质进行等离子体蚀刻。