公开(公告)号：US4262296A

公开(公告)日：1981-04-14

申请号：US61450

申请日：1979-07-27

申请人： James R. Shealy ,  Bantval J. Baliga ,  Wirojana Tantraporn ,  Peter V. Gray

发明人： James R. Shealy ,  Bantval J. Baliga ,  Wirojana Tantraporn ,  Peter V. Gray

IPC分类号： H01L29/80 ,  H01L29/10 ,  H01L29/417 ,  H01L29/808 ,  H01L29/812 ,  H01L29/06

CPC分类号： H01L29/8122 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/8083

摘要： A high frequency field effect transistor of gallium arsenide or other III-V semiconductor compounds has a preferentially etched trapezoidal groove structure in the top surface which creates parallel trapezoidal semiconductor fingers that are wider at the top than at the bottom. Schottky gates or junction gates are fabricated within the grooves surrounding the elongated fingers. The vertical conducting channels between the gates are narrow leading to a high blocking gain, and more contact area is available at the top of the device.

摘要翻译： 砷化镓或其他III-V半导体化合物的高频场效应晶体管在顶表面具有优先蚀刻的梯形沟槽结构，其产生在顶部比底部更宽的平行梯形半导体指状物。 在围绕细长指状物的凹槽内制造肖特基门或结门。 栅极之间的垂直导电沟道窄，导致高的阻塞增益，并且在器件顶部有更多的接触面积。

公开(公告)号：US4343015A

公开(公告)日：1982-08-03

申请号：US149936

申请日：1980-05-14

申请人： Bantval J. Baliga ,  James R. Shealy

发明人： Bantval J. Baliga ,  James R. Shealy

IPC分类号： H01L21/338 ,  H01L29/10 ,  H01L29/423 ,  H01L29/812

CPC分类号： H01L29/66856 ,  H01L29/1025 ,  H01L29/42316 ,  H01L29/8122

摘要： Improved high frequency GaAs FETs have a higher breakdown voltage, lower input gate capacitance and lower source (or drain) resistance. A preferentially etched groove structure yields parallel trapezoidal semiconductor fingers that are wider at the top than at the bottom. Every finger intersects a high resistivity, semi-insulating region which surrounds the active device area and is fabricated by high energy particle bombardment. Metal gates are deposited within the grooves on three sides of the trapezoidal fingers.

摘要翻译： 改进的高频GaAs FET具有更高的击穿电压，较低的输入栅极电容和较低的源极（或漏极）电阻。 优先蚀刻的凹槽结构产生在顶部比底部更宽的平行梯形半导体指状物。 每个指状物与围绕有源器件区域的高电阻率半绝缘区域相交，并且通过高能量粒子轰击制造。 金属门沉积在梯形手指三侧的槽内。

公开(公告)号：US4883767A

公开(公告)日：1989-11-28

申请号：US220353

申请日：1988-07-14

申请人： Peter V. Gray ,  Bantval J. Baliga ,  Mike F. S. Chang ,  George C. Pifer

发明人： Peter V. Gray ,  Bantval J. Baliga ,  Mike F. S. Chang ,  George C. Pifer

IPC分类号： H01L21/033 ,  H01L21/331 ,  H01L21/332 ,  H01L21/336

CPC分类号： H01L29/66712 ,  H01L21/033 ,  H01L29/66333 ,  H01L29/66378

摘要： A self aligned method of fabricating a self aligned semiconductor device employs an initial step in which a first window having an inner perimeter and outer perimeter is opened through a first protective layer situated atop a semiconductor substrate, to divide the substrate into three separate zones. The window exposes a first surface portion of the semiconductor substrate and circumferentially defines or encompasses a second central portion of the protective layer as well as a second unexposed surface portion of the substrate. A third surface portion of the substrate lies beyond the outer perimeter of the first window. Precisely aligned substrate regions of the same or different conductivity type can be established by using differentially etchable materials to mask designated surface portions of the substrate.

摘要翻译： 制造自对准半导体器件的自对准方法采用初始步骤，其中通过位于半导体衬底顶部的第一保护层打开具有内周边和外周边的第一窗口，以将衬底分成三个独立的区域。 窗口露出半导体衬底的第一表面部分并周向地限定或包围保护层的第二中心部分以及衬底的第二未曝光表面部分。 基板的第三表面部分位于第一窗口的外周边之外。 可以通过使用差分可蚀刻材料掩蔽衬底的指定表面部分来建立相同或不同导电类型的精确对准的衬底区域。

公开(公告)号：US4567641A

公开(公告)日：1986-02-04

申请号：US650314

申请日：1984-09-12

申请人： Bantval J. Baliga ,  Peter V. Gray ,  Robert P. Love

发明人： Bantval J. Baliga ,  Peter V. Gray ,  Robert P. Love

IPC分类号： H01L21/306 ,  H01L21/308 ,  H01L21/331 ,  H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L29/739 ,  H01L29/78 ,  H01L21/441 ,  H01L21/465

CPC分类号： H01L21/30608 ,  H01L21/308 ,  H01L29/1095 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/41766 ,  H01L29/4975

摘要： An improved semiconductor device having a diffused region of reduced length and an improved method of fabricating such a semiconductor device are disclosed. The semiconductor device may be a MOSFET or an IGR, by way of example. In a form of the method of fabricating a MOSFET, an N.sup.+ SOURCE is diffused into a P BASE through a window of a diffusion mask. An anisotropic or directional etchant is applied to the N.sup.+ SOURCE through the same window. The etchant removes most of the N.sup.+ SOURCE, but allows shoulders thereof to remain intact. These shoulders, which form the completed N.sup.+ SOURCE regions, are of reduced length, greatly reducing the risk of turn-on of a parasitic bipolar transistor in the MOSFET. The risk of turn-on of a parasitic bipolar transistor in an IGR is similarly reduced, when the IGR is fabricated by the improved method.

摘要翻译： 公开了一种具有减小长度的扩散区域的改进的半导体器件和制造这种半导体器件的改进方法。 作为示例，半导体器件可以是MOSFET或IGR。 以制造MOSFET的方法的形式，N + SOURCE通过扩散掩模的窗口扩散到P BASE中。 各向异性或定向蚀刻剂通过相同的窗口施加到N + SOURCE。 蚀刻剂除去大部分N + SOURCE，但允许其肩部保持完整。 构成完成的N + SOURCE区域的这些肩部的长度减小，大大降低了MOSFET中寄生双极晶体管导通的风险。 当通过改进的方法制造IGR时，IGR中的寄生双极晶体管的导通的风险也同样降低。

公开(公告)号：US5493134A

公开(公告)日：1996-02-20

申请号：US338392

申请日：1994-11-14

申请人： Manoj Mehrotra ,  Bantval J. Baliga

发明人： Manoj Mehrotra ,  Bantval J. Baliga

IPC分类号： H01L29/739 ,  H01L29/745 ,  H01L29/747 ,  H01L29/749 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7455 ,  H01L29/7397 ,  H01L29/747 ,  H01L29/749

摘要： A bidirectional semiconductor switching device includes a semiconductor substrate having first and second device terminals on opposite faces thereof, a thyristor in the substrate for providing regenerative conduction in a first direction, between the first device terminal and the second device terminal, and an insulated-gate bipolar junction transistor (IGBT) in the substrate for providing nonregenerative conduction in a second opposite direction, between the second device terminal and the first device terminal. In particular, the switching device includes first and second adjacent trenches therein at a face and respective first and second insulated-gate field effect transistors (IGFETs) in the trenches for providing gate-controlled turn-on and turn-off of the thyristor and the IGBT, by being electrically connected in series therewith.

摘要翻译： 一种双向半导体开关器件，包括：在其相对面上具有第一和第二器件端子的半导体衬底，用于在第一器件端子和第二器件端子之间的第一方向上提供再生传导的衬底中的晶闸管，以及绝缘栅极 在第二器件端子和第一器件端子之间在第二相反方向提供非再生导通的衬底中的双极结型晶体管（IGBT）。 特别地，开关器件包括位于其中的第一和第二相邻沟槽以及沟槽中的相应的第一和第二绝缘栅场效应晶体管（IGFET），用于提供栅极控制的晶闸管的导通和截止，以及 IGBT通过与其串联电连接。

公开(公告)号：US5318915A

公开(公告)日：1994-06-07

申请号：US8203

申请日：1993-01-25

申请人： Bantval J. Baliga ,  Dev Alok ,  Mohit Bhatnagar

发明人： Bantval J. Baliga ,  Dev Alok ,  Mohit Bhatnagar

IPC分类号： H01L21/04 ,  H01L21/20

CPC分类号： H01L21/046 ,  Y10S438/931

摘要： A method for forming a p-n junction in silicon carbide includes the steps of amorphizing a portion of a monocrystalline silicon carbide substrate, implanting dopant ions into the amorphous portion of the substrate and then recrystallizing the amorphous portion to thereby form a substantially monocrystalline region including the dopant ions. In particular, the amorphizing step includes the steps of masking an area on the face of the monocrystalline silicon carbide substrate and then directing electrically inactive ions to the masked area so that an amorphous region in the substrate is formed. Accordingly, the amorphous region has sidewalls extending to the face that are substantially orthogonal to the bottom edge of the amorphous region. Once the amorphized region is defined, electrically active dopant ions are implanted into the amorphous region. The dopant ions are then diffused into the amorphous region and become uniformly distributed. Next, the doped amorphized region is recrystallized to obtain a substantially monocrystalline doped region. If the region surrounding the recrystallized region are of opposite conductivity type, a vertically walled p-n junction is formed.

摘要翻译： 用于在碳化硅中形成pn结的方法包括以下步骤：将单晶碳化硅衬底的一部分非晶化，将掺杂剂离子注入到衬底的非晶部分中，然后使非晶部分重结晶，从而形成包括掺杂剂的基本单晶区域 离子。 特别地，非晶化步骤包括以下步骤：掩蔽单晶碳化硅衬底的表面上的区域，然后将非活性离子引导到掩蔽区域，从而形成衬底中的非晶区域。 因此，非晶区域具有延伸到基本上正交于非晶区域的底部边缘的面的侧壁。 一旦定义了非晶化区域，则将电活性掺杂剂离子注入非晶区域。 然后掺杂剂离子扩散到非晶区域并变得均匀分布。 接下来，掺杂的非晶化区域被重结晶以获得基本单晶掺杂区域。 如果再结晶区域周围的区域具有相反的导电型，则形成垂直壁的p-n结。

公开(公告)号：US5294816A

公开(公告)日：1994-03-15

申请号：US897456

申请日：1992-06-10

申请人： Mallikarjunaswamy S. Shekar ,  Mahalingam Nandakumar ,  Bantval J. Baliga

发明人： Mallikarjunaswamy S. Shekar ,  Mahalingam Nandakumar ,  Bantval J. Baliga

IPC分类号： H01L29/745 ,  H01L29/749 ,  H01L23/48 ,  H01L29/74 ,  H01L29/76

CPC分类号： H01L29/749 ,  H01L29/7455 ,  H01L2924/0002

摘要： An emitter switched thyristor with base resistance control for preventing parasitic latch-up includes a P-N-P-N main thyristor with an N.sup.+ floating emitter for MOS-gated controlled turn-on and a lateral P-channel MOSFET for shunting hole current in a second base region to a P.sup.+ diverting region electrically connected to the cathode. The P-channel MOSFET is enabled by the application of a negative gate voltage to form a P-type inversion layer between the second base region and the P.sup.+ diverter region, thus reducing the resistance between the cathode and the second base region and raising the holding current of the emitter switched thyristor to above the operating current level. The formation of an alternative current path to the cathode has the further effect of reducing the forward bias across the base-emitter junction of an adjacent parasitic thyristor to thereby prevent the sustained regenerative action of the parasitic thyristor.

摘要翻译： 具有用于防止寄生闩锁的基极电阻控制的发射极开关晶闸管包括具有用于MOS门控控制导通的N +浮置发射极的PNPN主晶闸管和用于在第二基极区中的分流电流的侧向P沟道MOSFET P +转移区电连接到阴极。 P沟道MOSFET通过施加负栅极电压来使能，以在第二基极区域和P +转移区域之间形成P型反型层，从而减小阴极和第二基极区域之间的电阻并且提高保持 发射极开关晶闸管的电流高于工作电流电平。 形成到阴极的替代电流路径具有减小相邻寄生晶闸管的基极 - 发射极结两端的正向偏压的进一步的效果，从而防止寄生晶闸管的持续再生作用。

公开(公告)号：US4982260A

公开(公告)日：1991-01-01

申请号：US415850

申请日：1989-10-02

申请人： Hsueh-Rong Chang ,  Bantval J. Baliga ,  David W. Tong

发明人： Hsueh-Rong Chang ,  Bantval J. Baliga ,  David W. Tong

IPC分类号： H01L29/861 ,  H01L29/87 ,  H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/861

摘要： A semiconductor power rectifier attains low forward voltage drop, low reverse leakage current and improved switching speed by utilizing Schottky contact regions in a p-i-n rectifier along with other means for reducing the required forward bias voltage. In a preferred embodiment, the other means for reducing the required forward bias voltage includes a respective trench between each respective pair of successively spaced current interruption means.

摘要翻译： 半导体功率整流器通过利用p-i-n整流器中的肖特基接触区域以及用于减少所需正向偏置电压的其它装置，获得低正向压降，低反向漏电流和提高的开关速度。 在优选实施例中，用于减小所需正向偏置电压的另一种装置包括在每个相应的一对连续间隔的电流中断装置之间的相应沟槽。

公开(公告)号：US4982258A

公开(公告)日：1991-01-01

申请号：US188888

申请日：1988-05-02

申请人： Bantval J. Baliga

发明人： Bantval J. Baliga

IPC分类号： H01L29/744 ,  H01L21/265 ,  H01L21/322 ,  H01L29/10 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749

CPC分类号： H01L29/102 ,  H01L21/26506 ,  H01L29/1016 ,  H01L29/7455

摘要： In a depletion mode thyristor of the type including a regenerative portion and a non-regenerative portion, the turn-off time for the thyristor is substantially reduced without producing a corresponding increase in the on-resistance of the device by providing a region of relatively low carrier lifetime in the non-regenerative portion of the device in the layer or layers in which charge storage limits the turn-off time for the device. Turn-off of the thyristor is accomplished by pinching off the regenerative portion, thereby diverting current into the low carrier lifetime non-regenerative portion.

公开(公告)号：US4980740A

公开(公告)日：1990-12-25

申请号：US329034

申请日：1989-03-27

申请人： Deva N. Pattanayak ,  Bantval J. Baliga

发明人： Deva N. Pattanayak ,  Bantval J. Baliga

IPC分类号： H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/1095 ,  H01L29/7395

摘要： A MOS-pilot structure for an IGT device consisting of a multiplicity of IGT cells interconnected in a lattice network includes a plurality of pilot emitter electrodes each in electrical contact with only at least one pilot emitter region of a first plurality of the multiplicity of IGT cells and electrically isolated from a common cathode electrode of the multiplicity of IGT cells. The plurality of pilot emitter electrodes are each electrically connected to a contact metal strip deposited on the substrate surface and spaced therefrom by a layer of insulation. The contact metal strip is connected to ground potential through a sense resistor for producing a sense voltage responsive only to the channel currents flowing through the at least one pilot emitter regions; therefore, a MOS pilot structure that utilizes only the MOS channel current to produce the sense voltage to cause turn-off of the IGT device at a large total current is disclosed. The MOS-pilot structure does not suffer from the avalanche breakdown problems during turn-off, that are associated with other prior art IGT pilot structures.