Process for depositing electrode with high effective work function
    3.
    发明授权
    Process for depositing electrode with high effective work function 有权
    具有高效功能的电极沉积工艺

    公开(公告)号:US09136180B2

    公开(公告)日:2015-09-15

    申请号:US13359385

    申请日:2012-01-26

    摘要: According to some embodiments, an electrode have a high effective work function is formed. The electrode may be the gate electrode of a transistor and may be formed on a high-k gate dielectric by depositing a first layer of conductive material, exposing that first layer to a hydrogen-containing gas, and depositing a second layer of conductive material over the first layer. The first layer may be deposited using a non-plasma process in which the substrate is not exposed to plasma or plasma-generated radicals. The hydrogen-containing gas to which the first layer is exposed may include an excited hydrogen species, which may be part of a hydrogen-containing plasma, and may be hydrogen-containing radicals. The first layer may also be exposed to oxygen before depositing the second layer. The work function of the gate electrode in the gate stack may be about 5 eV or higher in some embodiments.

    摘要翻译: 根据一些实施例,形成具有高有效功函数的电极。 电极可以是晶体管的栅极,并且可以通过沉积第一层导电材料,将第一层暴露于含氢气体,并将第二层导电材料沉积在高k栅极电介质上形成 第一层。 可以使用其中衬底不暴露于等离子体或等离子体产生的自由基的非等离子体工艺来沉积第一层。 第一层露出的含氢气体可以包括可以是含氢等离子体的一部分的被激发的氢物质,并且可以是含氢基团。 在沉积第二层之前,第一层也可能暴露于氧气。 在一些实施例中,栅极堆叠中的栅电极的功函数可以为约5eV或更高。

    METHOD OF FORMING NON-CONFORMAL LAYERS
    5.
    发明申请
    METHOD OF FORMING NON-CONFORMAL LAYERS 有权
    形成非一致层的方法

    公开(公告)号:US20100022099A1

    公开(公告)日:2010-01-28

    申请号:US12573008

    申请日:2009-10-02

    IPC分类号: H01L21/302

    摘要: In one aspect, non-conformal layers are formed by variations of plasma enhanced atomic layer deposition, where one or more of pulse duration, separation, RF power on-time, reactant concentration, pressure and electrode spacing are varied from true self-saturating reactions to operate in a depletion-effect mode. Deposition thus takes place close to the substrate surface but is controlled to terminate after reaching a specified distance into openings (e.g., deep DRAM trenches, pores, etc.). Reactor configurations that are suited to such modulation include showerhead, in situ plasma reactors, particularly with adjustable electrode spacing. In another aspect, alternately and sequentially contacting a substrate, the substrate including openings, with at least two different reactants, wherein an under-saturated dose of at least one of the reactants has been predetermined and the under-saturated dose is provided uniformly across the substrate surface, deposits a film that less than fully covers surfaces of the openings, leading to depletion effects in less accessible regions on the substrate surface

    摘要翻译: 在一个方面,通过等离子体增强原子层沉积的变化形成非共形层,其中脉冲持续时间,分离,RF功率导通时间,反应物浓度,压力和电极间距中的一个或多个从真实的自饱和反应变化 以耗尽效应模式运行。 因此,沉积物靠近基底表面发生,但是在到达开口(例如,深的DRAM沟槽,孔隙等)中的特定距离之后被控制终止。 适用于这种调制的反应器配置包括喷头,原位等离子体反应器,特别是具有可调节的电极间距。 在另一方面,交替地和顺序地接触基底,包括开口的基底与至少两种不同的反应物接触,其中至少一种反应物的饱和剂量已被预先确定,并且不饱和剂量被均匀地提供在 衬底表面沉积小于完全覆盖开口表面的膜,导致在衬底表面上较不易接近的区域中的耗尽效应

    Method for adjusting the threshold voltage of a gate stack of a PMOS device
    7.
    发明授权
    Method for adjusting the threshold voltage of a gate stack of a PMOS device 有权
    用于调整PMOS器件的栅极堆叠的阈值电压的方法

    公开(公告)号:US08399344B2

    公开(公告)日:2013-03-19

    申请号:US12898911

    申请日:2010-10-06

    IPC分类号: H01L21/28

    摘要: A method for fabricating a semiconductor device comprising a gate stack of a gate dielectric and a gate electrode, the method including forming a gate dielectric layer over a semiconductor substrate the gate dielectric layer being a metal oxide or semimetal oxide having a first electronegativity; forming a dielectric VT adjustment layer, the dielectric VT adjustment layer being a metal oxide or semimetal oxide having a second electronegativity; and forming a gate electrode over the gate dielectric layer and the VT adjustment layer; wherein the Effective Work Function of said gate stack is tuned to a desired value by tuning the thickness and composition of the dielectric VT adjustment layer and wherein the second electronegativity value is higher than both the first electronegativity value and the electronegativity of Al2O3.

    摘要翻译: 一种用于制造半导体器件的方法,包括栅极电介质和栅电极的栅极堆叠,所述方法包括在半导体衬底上形成具有第一电负性的金属氧化物或半金属氧化物的栅极介电层; 形成电介质VT调整层,电介质VT调整层是具有第二电负性的金属氧化物或半金属氧化物; 以及在所述栅极电介质层和所述VT调整层上形成栅电极; 其中所述栅极叠层的有效功函数通过调谐介电VT调整层的厚度和组成而被调谐到期望值,并且其中第二电负性值高于第一电负性值和Al 2 O 3的电负性。

    PROCESS FOR DEPOSITING ELECTRODE WITH HIGH EFFECTIVE WORK FUNCTION
    8.
    发明申请
    PROCESS FOR DEPOSITING ELECTRODE WITH HIGH EFFECTIVE WORK FUNCTION 有权
    具有高效工作功能沉积电极的工艺

    公开(公告)号:US20120309181A1

    公开(公告)日:2012-12-06

    申请号:US13359385

    申请日:2012-01-26

    IPC分类号: H01L21/28

    摘要: According to some embodiments, an electrode have a high effective work function is formed. The electrode may be the gate electrode of a transistor and may be formed on a high-k gate dielectric by depositing a first layer of conductive material, exposing that first layer to a hydrogen-containing gas, and depositing a second layer of conductive material over the first layer. The first layer may be deposited using a non-plasma process in which the substrate is not exposed to plasma or plasma-generated radicals. The hydrogen-containing gas to which the first layer is exposed may include an excited hydrogen species, which may be part of a hydrogen-containing plasma, and may be hydrogen-containing radicals. The first layer may also be exposed to oxygen before depositing the second layer. The work function of the gate electrode in the gate stack may be about 5 eV or higher in some embodiments.

    摘要翻译: 根据一些实施例,形成具有高有效功函数的电极。 电极可以是晶体管的栅极,并且可以通过沉积第一层导电材料,将第一层暴露于含氢气体,并将第二层导电材料沉积在高k栅极电介质上形成 第一层。 可以使用其中衬底不暴露于等离子体或等离子体产生的自由基的非等离子体工艺来沉积第一层。 第一层露出的含氢气体可以包括可以是含氢等离子体的一部分的被激发的氢物质,并且可以是含氢基团。 在沉积第二层之前,第一层也可能暴露于氧气。 在一些实施例中,栅极堆叠中的栅电极的功函数可以为约5eV或更高。

    METHOD FOR ADJUSTING THE THRESHOLD VOLTAGE OF A GATE STACK OF A PMOS DEVICE
    9.
    发明申请
    METHOD FOR ADJUSTING THE THRESHOLD VOLTAGE OF A GATE STACK OF A PMOS DEVICE 有权
    调整PMOS器件门极电压的方法

    公开(公告)号:US20110081775A1

    公开(公告)日:2011-04-07

    申请号:US12898911

    申请日:2010-10-06

    IPC分类号: H01L21/28

    摘要: A method for fabricating a semiconductor device comprising a gate stack of a gate dielectric and a gate electrode, the method including forming a gate dielectric layer over a semiconductor substrate the gate dielectric layer being a metal oxide or semimetal oxide having a first electronegativity; forming a dielectric VT adjustment layer, the dielectric VT adjustment layer being a metal oxide or semimetal oxide having a second electronegativity; and forming a gate electrode over the gate dielectric layer and the VT adjustment layer; wherein the Effective Work Function of said gate stack is tuned to a desired value by tuning the thickness and composition of the dielectric VT adjustment layer and wherein the second electronegativity value is higher than both the first electronegativity value and the electronegativity of Al2O3

    摘要翻译: 一种用于制造半导体器件的方法,包括栅极电介质和栅电极的栅极堆叠,所述方法包括在半导体衬底上形成具有第一电负性的金属氧化物或半金属氧化物的栅极介电层; 形成电介质VT调整层,电介质VT调整层是具有第二电负性的金属氧化物或半金属氧化物; 以及在所述栅极电介质层和所述VT调整层上形成栅电极; 其中通过调谐介电VT调整层的厚度和组成将所述栅极叠层的有效功函数调谐到期望值,并且其中第二电负性值高于Al2O3的第一电负性值和电负性

    ALD of metal silicate films
    10.
    发明授权
    ALD of metal silicate films 有权
    金属硅酸盐膜的ALD

    公开(公告)号:US07795160B2

    公开(公告)日:2010-09-14

    申请号:US11490875

    申请日:2006-07-21

    IPC分类号: H01L21/31

    摘要: Methods for forming metal silicate films are provided. The methods comprise contacting a substrate with alternating and sequential vapor phase pulses of a metal source chemical, a silicon source chemical and an oxidizing agent. In preferred embodiments, an alkyl amide metal compound and a silicon halide compound are used. Methods according to preferred embodiments can be used to form hafnium silicate and zirconium silicate films with substantially uniform film coverages on substrate surfaces comprising high aspect ratio features (e.g., vias and/or trenches).

    摘要翻译: 提供了形成金属硅酸盐膜的方法。 所述方法包括使基板与金属源化学品,硅源化学品和氧化剂的交替和顺序的气相脉冲接触。 在优选的实施方案中,使用烷基酰胺金属化合物和卤化硅化合物。 根据优选实施方案的方法可以用于在包含高纵横比特征(例如,通孔和/或沟槽)的衬底表面上形成具有基本上均匀的薄膜覆盖率的硅酸铪硅酸盐膜和硅酸锆膜。