摘要:
A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.
摘要:
A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.
摘要:
A method of manufacturing a wafer level package including: separating chips by dicing a wafer; forming a removable resin layer in a space between the separated chips and at upper parts thereof; separating the chips by dicing the removable resin layer; mounting the chips separated in a state of being surrounded by the removable resin layer, on a carrier plate; forming a molding material on the carrier plate to cover the removable resin layer; separating the carrier plate from the chips; forming a dielectric layer having redistribution lines connected to the chips, on the chips exposed by separating the carrier plate; and forming a solder resist layer on the dielectric layer to expose portions of the redistribution lines.
摘要:
A wafer level package includes a chip, a removable resin layer, a molding material, a dielectric layer, redistribution lines and a solder resist. The removable resin layer is formed to surround side surfaces and a lower surface of the chip. The molding material is formed on the lower surface of the removable resin layer. The dielectric layer is formed over the removable resin layer including the chip and having via holes to expose portions of the chip. The redistribution lines are formed on the dielectric layer including insides of the via holes to be connected to the chip. The solder resist layer is formed on the dielectric layer to expose portions of the redistribution lines.
摘要:
Disclosed herein are a wafer level package for heat dissipation and a method of manufacturing the same. The wafer level package includes a heat dissipation plate including a cavity and a hole, a die including a pad disposed in the cavity of the heat dissipation plate in a face-up manner, a thermal conductive adhesive disposed between the die and an inner wall of the cavity and disposed in the hole, and a redistribution layer connected at one end to the pad and at the other end extended. The wafer level package protects the die from external environments and enables the die to be easily flush with the heat dissipation plate.
摘要:
A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.
摘要:
Disclosed is a printed circuit board including a semiconductor chip, which includes a semiconductor chip having a connection pad, which is exposed, on the upper surface thereof, a first solder ball formed on the connection pad and having a first melting point, a printed circuit board having an external connection terminal formed at the outermost circuit layer thereof, and a second solder ball formed on the external connection terminal, connected to the first solder ball, and having a second melting point higher than the first melting point. In the printed circuit board including a semiconductor chip, the distance between the printed circuit board and the semiconductor chip is increased, thus realizing high resistance to flexure due to the difference in thermal expansion coefficient between the printed circuit board and the semiconductor chip.
摘要:
A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.
摘要:
Disclosed herein are a wafer level package for heat dissipation and a method of manufacturing the same. The wafer level package includes a heat dissipation plate including a cavity and a hole, a die including a pad disposed in the cavity of the heat dissipation plate in a face-up manner, a thermal conductive adhesive disposed between the die and an inner wall of the cavity and disposed in the hole, and a redistribution layer connected at one end to the pad and at the other end extended. The wafer level package protects the die from external environments and enables the die to be easily flush with the heat dissipation plate.
摘要:
Disclosed herein are a die package and a method of manufacturing the die package. A solder layer is formed on a lower surface of a die. The die is self-aligned and attached to a support plate using surface tension between the solder layer and a metal layer of the support plate, thus reducing attachment lead time of the die.