摘要:
Control signals are input to the gates of a P-MOS transistor and an N-MOS transistor of a CMOS drive circuit from respective control signal generating sections. The CMOS drive circuit drives a piezoelectric member as a capacitive element and the piezoelectric element is used in an ink jet head. A substrate of the P-MOS transistor is provided with a voltage higher than a power supply of the CMOS drive circuit. A first potential difference is supplied between terminals of the piezoelectric element and thereafter, a second potential difference of a polarity opposite to the first potential difference is further supplied between the terminals. A discharge operation is inserted in a time period from the time when supply of the first potential difference is completed till the supply of the second difference gets started. The discharge operating time period is set to a proper value at which a desired operating speed, high reliability and low power consumption are achieved.
摘要:
A function ally gradient composite material containing copper and carbon as main components and having a predetermined shape, in which the composition ratio of the copper to the carbon in the material continuously varies in at least one predetermined direction. The material is manufactured, for example, by impregnating carbon felt with a resin and thermo-compressively molding the impregnated felt (step S101), carbonizing the resin by baking (step S102) to provide a preformed carbon material (step S104). Pyrolytic carbon is thereafter deposited in the preformed carbon material by the CVI method (step S105) to provide a carbon material having the bulk density varying in a predetermined direction (step S107). After the wettability of the carbon material against copper is improved by siliconization (step S108), pores of the carbon material are impregnated with copper (step S109) to obtain a functionally gradient composite material of copper and carbon.
摘要:
An improved mutant vaccinia virus providing a pock and plaque size on RK13 cells that is approximately the same as those of the Lister original, having a proliferation potency on YTV cells that is approximately the same as that of the Lister original, and having a neurovirulence, assessed by a recovery of an intrabrain virus, that is lower than that of the Lister original; and a process for the production thereof.
摘要:
A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.
摘要:
A method for immobilizing living microorganisms includes a step (1) of disposing a solution containing microorganisms as an electrolyte on the surface of a substrate at least one portion of which is an electrode, and applying a constant potential to the electrode to cause at least a portion of the microorganisms to attach to the surface of the substrate. The constant potential in step (1) is greater than −0.5 V but not greater than −0.2 V (vs Ag/AgCl) or greater than +0.2 V but not greater than +0.4 V (vs Ag/AgCl). The electrolyte in step (1) does not contain a source of nutrition for the microorganisms.
摘要:
A nonvolatile memory device has a memory cell having its gate connected to a word line, its source connected to a ground potential and its drain connected to a power supply voltage via a bit line and a dummy cell having its gate connected to the word line, its source connected to the source potential and its drain connected to the power supply voltage via a dummy bit line. The bit line and the dummy bit line are connected to reset and set terminals of a sense amplifier circuit comprising a flip-flop circuit and a latch type of sense amplifier. The conductance of the dummy cell is made smaller than that of the memory cell so that the speed at which the potential on the bit line is lowered depends on the state of injection of electrons into the memory cell as compared with the speed at which the potential on the dummy bit line at a time of reading data. The flip-flop circuit is reset or set in accordance with the speed at which the potential on the bit line is lowered and then the latch type of sense amplifier operates to latch the output of the flip-flop circuit and output it as read data.
摘要:
A voltage multiplier for a use in a non-volatile semiconductor memory and operated at a low operation voltage with a reduced area comprising a plurality of cascade-connected basic circuits.
摘要:
In a nonvolatile semiconductor memory according to the invention, a power source voltage of 5 V used in an ordinary read mode is applied to a read line in the data read mode without changing its value. If a write line, a selection gate line, a control gate line, and a read line are respectively set at 0 V, 5 V, 0 V, and 5 V in the data read mode, the potential at an n-type diffusion layer becomes 0 V. In this case, the potential at the control gate line is 0 V, and the potential at a floating gate electrode becomes substantially 0 V. That is, an electric field is not applied to a thin insulating film located between the floating gate electrode and the n-type diffusion layer. As a result, electron injection and discharge due to the tunnel effect do not occur.
摘要:
A neutron absorbing pin including at least, a neutron absorber, a thin-wall pipe surrounding the neutron absorber, and a cladding disposed at a distance from the thin-wall pipe. In the neutron absorbing pin, the difference between the coefficient of thermal expansion (.alpha.1) of the neutron absorber and the coefficient of thermal expansion (.alpha.2) of the thin-wall pipe has an absolute value of .vertline..alpha.2-.alpha.1.vertline..ltoreq.10.times.10.sup.-6 /K.
摘要:
A semiconductor memory integrated circuit is made up of a decoder, a memory matrix, and a decode output buffer selectively receiving a first or second power source voltage. The decode output buffer is provided between the decoder and the memory matrix, and includes an inverter circuit for inverting the output signal of the decoder, and a MOS transistor of a depletion mode, the gate of which is connected to the output terminal of the inverter, the first end of which is connected to a supply node of the first or second power source voltage, and the second end of which is connected to a power voltage supply node of the inverter circuit.