公开(公告)号：US20110068455A1

公开(公告)日：2011-03-24

申请号：US12565355

申请日：2009-09-23

申请人： Jun Yong WANG ,  Geng-Shin Shen

发明人： Jun Yong WANG ,  Geng-Shin Shen

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L24/13 ,  H01L21/56 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： This invention relates to a packaging structure and method for manufacturing the packaging structure. The packaging structure comprises a substrate film, a plurality of chips, a compound resin layer and a support layer. The substrate film is formed with circuits having a plurality of terminals exposed from a solder mask. The chips, each of which has a plurality of pads, under bump metals (UBMs) formed on the pads, and composite bumps disposed onto the UBMs, are bonded onto the substrate film to form the first tape. The second tape comprises the support layer and the compound resin layer formed on the support layer. The first tape and the second tape are both in reel-form and are expanded towards a pair of rollers to be heated and pressurized for encapsulating the chips.

摘要翻译： 本发明涉及用于制造包装结构的包装结构和方法。 包装结构包括基底膜，多个芯片，复合树脂层和支撑层。 衬底膜由具有从焊料掩模暴露的多个端子的电路形成。 每个芯片具有多个焊盘，形成在焊盘上的凸块下金属（UBM）和设置在UBM上的复合凸块相连接，形成第一条带。 第二带包括支撑层和形成在支撑层上的复合树脂层。 第一带和第二带都是卷状的并且朝向一对辊膨胀，以被加热和加压以封装芯片。

公开(公告)号：US20120074402A1

公开(公告)日：2012-03-29

申请号：US13308828

申请日：2011-12-01

申请人： Jun-Yong Wang ,  Geng-Shin Shen

发明人： Jun-Yong Wang ,  Geng-Shin Shen

IPC分类号： H01L23/485

CPC分类号： H01L24/13 ,  H01L21/56 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： This invention relates to a packaging structure and method for manufacturing the packaging structure. The packaging structure comprises a substrate film, a plurality of chips, a compound resin layer and a support layer. The substrate film is formed with circuits having a plurality of terminals exposed from a solder mask. The chips, each of which has a plurality of pads, under bump metals (UBMs) formed on the pads, and composite bumps disposed onto the UBMs, are bonded onto the substrate film to form the first tape. The second tape comprises the support layer and the compound resin layer formed on the support layer. The first tape and the second tape are both in reel-form and are expanded towards a pair of rollers to be heated and pressurized for encapsulating the chips.

摘要翻译： 本发明涉及用于制造包装结构的包装结构和方法。 包装结构包括基底膜，多个芯片，复合树脂层和支撑层。 衬底膜由具有从焊料掩模暴露的多个端子的电路形成。 每个芯片具有多个焊盘，形成在焊盘上的凸块下金属（UBM）和设置在UBM上的复合凸块相连接，形成第一条带。 第二带包括支撑层和形成在支撑层上的复合树脂层。 第一带和第二带都是卷状的并且朝向一对辊膨胀，以被加热和加压以封装芯片。

公开(公告)号：US08093106B2

公开(公告)日：2012-01-10

申请号：US12565355

申请日：2009-09-23

申请人： Jun-Yong Wang ,  Geng-Shin Shen

发明人： Jun-Yong Wang ,  Geng-Shin Shen

IPC分类号： H01L21/00

CPC分类号： H01L24/13 ,  H01L21/56 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： This invention relates to a packaging structure and method for manufacturing the packaging structure. The packaging structure comprises a substrate film, a plurality of chips, a compound resin layer and a support layer. The substrate film is formed with circuits having a plurality of terminals exposed from a solder mask. The chips, each of which has a plurality of pads, under bump metals (UBMs) formed on the pads, and composite bumps disposed onto the UBMs, are bonded onto the substrate film to form the first tape. The second tape comprises the support layer and the compound resin layer formed on the support layer. The first tape and the second tape are both in reel-form and are expanded towards a pair of rollers to be heated and pressurized for encapsulating the chips.

摘要翻译： 本发明涉及用于制造包装结构的包装结构和方法。 包装结构包括基底膜，多个芯片，复合树脂层和支撑层。 衬底膜由具有从焊料掩模暴露的多个端子的电路形成。 每个芯片具有多个焊盘，形成在焊盘上的凸块下金属（UBM）和设置在UBM上的复合凸块相连接，形成第一条带。 第二带包括支撑层和形成在支撑层上的复合树脂层。 第一带和第二带都是卷状的并且朝向一对辊膨胀，以被加热和加压以封装芯片。

公开(公告)号：US08736060B2

公开(公告)日：2014-05-27

申请号：US13308828

申请日：2011-12-01

申请人： Jun-Yong Wang ,  Geng-Shin Shen

发明人： Jun-Yong Wang ,  Geng-Shin Shen

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L21/56 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： This invention relates to a packaging structure and method for manufacturing the packaging structure. The packaging structure comprises a substrate film, a plurality of chips, a compound resin layer and a support layer. The substrate film is formed with circuits having a plurality of terminals exposed from a solder mask. The chips, each of which has a plurality of pads, under bump metals (UBMs) formed on the pads, and composite bumps disposed onto the UBMs, are bonded onto the substrate film to form the first tape. The second tape comprises the support layer and the compound resin layer formed on the support layer. The first tape and the second tape are both in reel-form and are expanded towards a pair of rollers to be heated and pressurized for encapsulating the chips.

摘要翻译： 本发明涉及用于制造包装结构的包装结构和方法。 包装结构包括基底膜，多个芯片，复合树脂层和支撑层。 衬底膜由具有从焊料掩模暴露的多个端子的电路形成。 每个芯片具有多个焊盘，形成在焊盘上的凸块下金属（UBM）和设置在UBM上的复合凸块相连接，形成第一条带。 第二带包括支撑层和形成在支撑层上的复合树脂层。 第一带和第二带都是卷状的并且朝向一对辊膨胀，以被加热和加压以封装芯片。

公开(公告)号：US08712932B2

公开(公告)日：2014-04-29

申请号：US13543421

申请日：2012-07-06

申请人： Geng-Shin Shen ,  Hui-Chung Che

发明人： Geng-Shin Shen ,  Hui-Chung Che

IPC分类号： G06F15/18

CPC分类号： G06Q50/184 ,  G06F2216/11

摘要： A computer implemented apparatus for automatically generating and filtering creative proposals is disclosed. Particularly, the computer implemented apparatus automatically generates all possible featured component code sets which corresponding to all possible featured components, and compares them to the prior art code sets which corresponding to the prior objects. Thereby, the novel code sets which corresponding to the novel creative proposals are rapidly filtered out. The computer implemented apparatus comprises a standard component database, a permutation and combination module, a featured component code set database, a prior art code set database, a matching module, a sifting module and an output module.

摘要翻译： 公开了一种用于自动生成和过滤创意提案的计算机实现的装置。 特别地，计算机实现的装置自动生成对应于所有可能的特征分量的所有可能的特征分量代码集，并将它们与对应于现有对象的现有技术代码集进行比较。 因此，与新颖的创意提案相对应的新颖代码集被快速过滤掉。 计算机实现的装置包括标准组件数据库，置换和组合模块，特征组件代码集数据库，现有技术代码集数据库，匹配模块，筛选模块和输出模块。

公开(公告)号：US08058109B2

公开(公告)日：2011-11-15

申请号：US12899530

申请日：2010-10-06

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L21/00

CPC分类号： H01L23/49894 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/90 ,  H01L24/97 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83855 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/00

摘要： The present invention provides a method for manufacturing a semiconductor structure, —including—the following steps of: forming a substrate having a package array; forming a thermosetting non-conductive layer covering the substrate; partially solidifying the thermosetting non-conductive layer to form a semi-solid non-conductive layer; connecting chips to the package array on the substrate; pressing and heating the chips and the substrate so that the semi-solid non-conductive layer adheres with the chips and the substrate; pre-heating an encapsulant preformed on a metal layer; covering the chips on the substrate with the encapsulant; and solidifying the encapsulant to completely cover the chips on the substrate. The present invention can reduce use of gold to lower the manufacturing cost and can also improve the heat conduction efficiency of the semiconductor structure to enhance operational stability of the chips.

摘要翻译： 本发明提供一种制造半导体结构的方法，包括以下步骤：形成具有封装阵列的衬底; 形成覆盖所述基板的热固性非导电层; 部分固化热固性非导电层以形成半固体非导电层; 将芯片连接到衬底上的封装阵列; 挤压和加热芯片和基板，使得半固体非导电层与芯片和基板粘合; 预热在金属层上预成型的密封剂; 用密封剂覆盖基板上的芯片; 并固化所述密封剂以完全覆盖所述基板上的所述芯片。 本发明可以减少金的使用以降低制造成本，并且还可以提高半导体结构的热传导效率，以提高芯片的操作稳定性。

公开(公告)号：US20110207262A1

公开(公告)日：2011-08-25

申请号：US12899530

申请日：2010-10-06

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L21/603

CPC分类号： H01L23/49894 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/90 ,  H01L24/97 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83855 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/00

摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps of: forming a substrate having a package array, wherein the package array has a plurality of contact pads and a protection layer, and the plurality of contact pads are exposed to the outer side of the protection layer; forming a thermosetting non-conductive layer covering the substrate; partially solidifying the thermosetting non-conductive layer to form a semi-solid non-conductive layer; connecting chips to the package array on the substrate, wherein each of the chips has an active surface, a plurality of chip pads and a plurality of composite bumps, the chip pads are formed on the active surface, and the composite bumps are formed on the chip pads so that the composite bumps electrically connect to each of the contact pads; pressing and heating the chips and the substrate so that the semi-solid non-conductive layer adheres with the chips and the substrate; pre-heating an encapsulant preformed on a metal layer; covering the chips on the substrate with the encapsulant; and solidifying the encapsulant to completely cover the chips on the substrate. The present invention can reduce use of gold to lower the manufacturing cost and can also improve the heat conduction efficiency of the semiconductor structure to enhance operational stability of the chips.

摘要翻译： 本发明提供一种制造半导体结构的方法，包括以下步骤：形成具有封装阵列的衬底，其中所述封装阵列具有多个接触焊盘和保护层，并且所述多个接触焊盘暴露于 保护层的外侧; 形成覆盖所述基板的热固性非导电层; 部分固化热固性非导电层以形成半固体非导电层; 将芯片连接到基板上的封装阵列，其中每个芯片具有活性表面，多个芯片焊盘和多个复合凸块，在有源表面上形成芯片焊盘，并且复合凸块形成在 芯片焊盘，使得复合凸块电连接到每个接触焊盘; 挤压和加热芯片和基板，使得半固体非导电层与芯片和基板粘合; 预热在金属层上预成型的密封剂; 用密封剂覆盖基板上的芯片; 并固化所述密封剂以完全覆盖所述基板上的所述芯片。 本发明可以减少金的使用以降低制造成本，并且还可以提高半导体结构的热传导效率，以提高芯片的操作稳定性。

公开(公告)号：US07960214B2

公开(公告)日：2011-06-14

申请号：US12169132

申请日：2008-07-08

申请人： Geng-Shin Shen ,  David Wei Wang

发明人： Geng-Shin Shen ,  David Wei Wang

IPC分类号： H01L21/44

CPC分类号： H01L24/16 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A fabricating process of chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate or on the second substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the first B-staged adhesive layer and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

摘要翻译： 提供了芯片封装结构的制造工艺。 首先，提供具有多个第一接合焊盘的第一基板和具有多个第二接合焊盘的第二基板，其中在第一基板的第一接合焊盘上形成多个凸点。 在第一基板上或第二基板上形成第一两级粘合剂层，并且被B阶段化以形成第一B阶粘合剂层。 在第一B阶粘合剂层上形成第二两层粘合剂层，并且被B阶段化以形成第二B阶粘合剂层。 然后，第一基板和第二基板经由第一B阶粘合剂层和第二B阶粘合剂层接合，使得每个第一接合焊盘分别经由第一接合焊盘中的一个电连接到第二接合焊盘中的一个 颠簸

公开(公告)号：US07915690B2

公开(公告)日：2011-03-29

申请号：US12635388

申请日：2009-12-10

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/34 ,  H01L23/48

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2224/82

摘要： A die rearrangement package structure is provided, which includes a die that having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover a die and the active surface being exposed; a polymer material with at least one slit is provided to cover the active surface and the pads is exposed from said slits; one ends of a plurality of metal traces is electrically connected to each pads; a protective layer is provided to cover the active surface of the dies and each metal traces, and the other ends of the metal traces being exposed; a plurality of connecting elements is electrically connected other ends of the metal traces, the characterized in that: the package body is a B-stage material.

摘要翻译： 提供了一种管芯重排封装结构，其包括具有活性表面和底表面的管芯，并且多个焊盘设置在有源表面上; 提供封装体以覆盖裸片并且所述有源表面被暴露; 提供具有至少一个狭缝的聚合物材料以覆盖有源表面，并且所述焊盘从所述狭缝暴露; 多个金属迹线的一端电连接到每个焊盘; 提供保护层以覆盖管芯的活性表面和每个金属迹线，并且金属迹线的另一端被暴露; 多个连接元件与金属迹线的另一端电连接，其特征在于：封装体是B级材料。

公开(公告)号：US07847414B2

公开(公告)日：2010-12-07

申请号：US12147929

申请日：2008-06-27

申请人： Geng-Shin Shen ,  David Wei Wang

发明人： Geng-Shin Shen ,  David Wei Wang

IPC分类号： H01L23/48 ,  H01L23/538 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-staged adhesive layer and a second B-staged adhesive layer is provided. The first substrate has a plurality of first bonding pads. The second substrate has a plurality of second bonding pads, and the second substrate is disposed above the first substrate. The bumps are disposed between the first substrate and the second substrate, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps. The first B-staged adhesive layer is adhered on the first substrate. The second B-staged adhesive layer is adhered between the first B-staged adhesive layer and the second substrate, wherein the first B-staged adhesive layer and the second B-staged adhesive layer encapsulate the bumps.

摘要翻译： 提供了包括第一基板，第二基板，多个凸块，第一B阶粘合剂层和第二B阶粘合剂层的芯片封装结构。 第一基板具有多个第一接合焊盘。 第二基板具有多个第二接合焊盘，第二基板设置在第一基板的上方。 所述凸块设置在所述第一基板和所述第二基板之间，其中所述第一接合焊盘中的每一个分别经由所述凸块之一电连接到所述第二接合焊盘中的一个。 第一B级粘合剂层粘附在第一基底上。 第二B阶粘合剂层粘附在第一B阶粘合剂层和第二基底之间，其中第一B阶粘合剂层和第二B阶粘合剂层包封凸块。