公开(公告)号：US06965166B2

公开(公告)日：2005-11-15

申请号：US10373692

申请日：2003-02-27

申请人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Koji Yamamoto

发明人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Koji Yamamoto

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L21/98 ,  H01L23/31 ,  H01L23/36 ,  H01L23/48 ,  H01L23/485 ,  H01L23/498 ,  H01L25/065 ,  H01L29/06

CPC分类号： H01L24/13 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/17517 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013

摘要： A semiconductor device including a first semiconductor chip, a second semiconductor chip bonded to the first semiconductor chip in a stacked relation, and a registration structure which causes the first and second semiconductor chips to be positioned with respect to each other by depression-projection engagement therebetween. The registration structure includes, for example, a registration recess provided on a surface of the first semiconductor chip, and a registration projection provided on a surface of the second semiconductor chip for engagement with the registration recess. The registration projection may be a spherical member provided on the surface of the second semiconductor chip.

摘要翻译： 一种半导体器件，包括第一半导体芯片，以堆叠关系结合到第一半导体芯片的第二半导体芯片，以及配准结构，其使得第一半导体芯片和第二半导体芯片通过其间的凹凸突起相互相对于彼此定位 。 配准结构包括例如设置在第一半导体芯片的表面上的配准凹槽以及设置在第二半导体芯片的表面上用于与配准凹槽接合的配准突起。 配准突起可以是设置在第二半导体芯片的表面上的球形部件。

公开(公告)号：US07307349B2

公开(公告)日：2007-12-11

申请号：US11150129

申请日：2005-06-13

申请人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Koji Yamamoto

发明人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Koji Yamamoto

IPC分类号： H01L23/52

CPC分类号： H01L24/13 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/17517 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013

摘要： A semiconductor device including a first semiconductor chip, a second semiconductor chip bonded to the first semiconductor chip in a stacked relation, and a registration structure which causes the first and second semiconductor chips to be positioned with respect to each other by depression-projection engagement therebetween. The registration structure includes, for example, a registration recess provided on a surface of the first semiconductor chip, and a registration projection provided on a surface of the second semiconductor chip for engagement with the registration recess. The registration projection may be a spherical member provided on the surface of the second semiconductor chip.

摘要翻译： 一种半导体器件，包括第一半导体芯片，以堆叠关系结合到第一半导体芯片的第二半导体芯片，以及配准结构，其使得第一半导体芯片和第二半导体芯片通过其间的凹凸突起相互相对于彼此定位 。 配准结构包括例如设置在第一半导体芯片的表面上的配准凹槽以及设置在第二半导体芯片的表面上用于与配准凹槽接合的配准突起。 配准突起可以是设置在第二半导体芯片的表面上的球形部件。

公开(公告)号：US20050253274A1

公开(公告)日：2005-11-17

申请号：US11150129

申请日：2005-06-13

申请人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Koji Yamamoto

发明人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Koji Yamamoto

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L21/98 ,  H01L23/31 ,  H01L23/36 ,  H01L23/48 ,  H01L23/485 ,  H01L23/498 ,  H01L25/065 ,  H01L29/06

CPC分类号： H01L24/13 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/17517 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013

摘要： A semiconductor device including a first semiconductor chip, a second semiconductor chip bonded to the first semiconductor chip in a stacked relation, and a registration structure which causes the first and second semiconductor chips to be positioned with respect to each other by depression-projection engagement therebetween. The registration structure includes, for example, a registration recess provided on a surface of the first semiconductor chip, and a registration projection provided on a surface of the second semiconductor chip for engagement with the registration recess. The registration projection may be a spherical member provided on the surface of the second semiconductor chip.

摘要翻译： 一种半导体器件，包括第一半导体芯片，以堆叠关系结合到第一半导体芯片的第二半导体芯片，以及配准结构，其使得第一半导体芯片和第二半导体芯片通过其间的凹凸突起相互相对于彼此定位 。 配准结构包括例如设置在第一半导体芯片的表面上的配准凹槽以及设置在第二半导体芯片的表面上用于与配准凹槽接合的配准突起。 配准突起可以是设置在第二半导体芯片的表面上的球形部件。

公开(公告)号：US06869829B2

公开(公告)日：2005-03-22

申请号：US10211308

申请日：2002-08-05

申请人： Junichi Hikita ,  Koji Yamamoto ,  Isamu Nishimura ,  Nobuhisa Kumamoto

发明人： Junichi Hikita ,  Koji Yamamoto ,  Isamu Nishimura ,  Nobuhisa Kumamoto

IPC分类号： H01L23/544 ,  H01L21/60

CPC分类号： H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15151 ,  Y10S438/975 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor chip (3) to be positioned with a front face thereof downward for formation of a chip-on-chip structure has electrode marks (35) provided on a back face (34) thereof. The electrode marks (35) are respectively provided in association with a plurality of electrodes (33) provided on the front face (31) of the semiconductor chip in the same arrangement as the arrangement of the electrodes (33). The arrangement of the electrode marks (35) represents the arrangement of the electrodes (33) on the front face (31) when viewed from the side of the back face (34) of the semiconductor chip 3. Therefore, the semiconductor chip (3) can easily be positioned with the front face downward on the basis of the electrode marks (35).

摘要翻译： 为了形成片上芯片结构，其前表面向下定位的半导体芯片（3）具有设置在其背面（34）上的电极标记（35）。 电极标记（35）与设置在半导体芯片的正面（31）上的多个电极（33）分别设置成与电极（33）的布置相同的布置。 电极标记（35）的布置表示从半导体芯片3的背面（34）的侧面观察时的正面（31）上的电极（33）的配置。因此，半导体芯片（3） ）可以根据电极标记（35）容易地将前表面向下定位。

公开(公告)号：US06476499B1

公开(公告)日：2002-11-05

申请号：US09499579

申请日：2000-02-07

申请人： Junichi Hikita ,  Koji Yamamoto ,  Isamu Nishimura ,  Nobuhisa Kumamoto

发明人： Junichi Hikita ,  Koji Yamamoto ,  Isamu Nishimura ,  Nobuhisa Kumamoto

IPC分类号： H01L2352

CPC分类号： H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15151 ,  Y10S438/975 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor chip (3) to be positioned with a front face thereof downward for formation of a chip-on-chip structure has electrode marks (35) provided on a back face (34) thereof. The electrode marks (35) are respectively provided in association with a plurality of electrodes (33) provided on the front face (31) of the semiconductor chip in the same arrangement as the arrangement of the electrodes (33). The arrangement of the electrode marks (35) represents the arrangement of the electrodes (33) on the front face (31) when viewed from the side of the back face (34) of the semiconductor chip 3. Therefore, the semiconductor chip (3) can easily be positioned with the front face downward on the basis of the electrode marks (35).

摘要翻译： 为了形成片上芯片结构，其前表面向下定位的半导体芯片（3）具有设置在其背面（34）上的电极标记（35）。 电极标记（35）与设置在半导体芯片的正面（31）上的多个电极（33）分别设置成与电极（33）的布置相同的布置。 电极标记（35）的布置表示从半导体芯片3的背面（34）的侧面观察时的正面（31）上的电极（33）的配置。因此，半导体芯片（3） ）可以根据电极标记（35）容易地将前表面向下定位。

公开(公告)号：US06838312B2

公开(公告)日：2005-01-04

申请号：US10314289

申请日：2002-12-09

申请人： Junichi Hikita ,  Koji Yamamoto

发明人： Junichi Hikita ,  Koji Yamamoto

IPC分类号： H01L25/18 ,  H01L23/02 ,  H01L25/065 ,  H01L25/07 ,  H01L21/44

CPC分类号： H01L25/0655 ,  H01L2224/16225

摘要： A semiconductor device having a plurality of semiconductor chips respectively joined to predetermined positions on a surface of a solid, and a frame holding the plurality of semiconductor chips in a relative positional relationship corresponding to joint positions on the surface of the solid. The solid may be another semiconductor chip or a wiring board. The plurality of semiconductor chips may be bonded to a surface, opposite to the surface, of the solid, of the frame. The plurality of semiconductor chips may be respectively fitted in through holes formed in the frame.

公开(公告)号：US06717244B1

公开(公告)日：2004-04-06

申请号：US09511108

申请日：2000-02-23

申请人： Junichi Hikita ,  Koji Yamamoto

发明人： Junichi Hikita ,  Koji Yamamoto

IPC分类号： H01L2302

CPC分类号： H01L25/0655 ,  H01L2224/16225

摘要： A semiconductor device having a plurality of semiconductor chips respectively joined to predetermined positions on a surface of a solid, and a frame holding the plurality of semiconductor chips in a relative positional relationship corresponding to joint positions on the surface of the solid. The solid may be another semiconductor chip or a wiring board. The plurality of semiconductor chips may be bonded to a surface, opposite to the surface of the solid, of the frame. The plurality of semiconductor chips may be respectively fitted in through holes formed in the frame.

摘要翻译： 具有分别连接到固体表面上的预定位置的多个半导体芯片的半导体器件和以与固体表面上的接合位置相对应的相对位置关系保持多个半导体芯片的框架。 固体可以是另一种半导体芯片或布线板。 多个半导体芯片可以结合到框架的与固体的表面相对的表面。 多个半导体芯片可以分别安装在形成在框架中的通孔中。

公开(公告)号：US09110458B2

公开(公告)日：2015-08-18

申请号：US13349783

申请日：2012-01-13

申请人： Akira Kimura ,  Koji Yamamoto ,  Katsuhiko Ono ,  Kimiyuki Nishimura ,  Kenichiro Ueno ,  Keiichi Nakamachi

发明人： Akira Kimura ,  Koji Yamamoto ,  Katsuhiko Ono ,  Kimiyuki Nishimura ,  Kenichiro Ueno ,  Keiichi Nakamachi

IPC分类号： G05B19/19 ,  G05D3/10 ,  G05B19/404

CPC分类号： G05B19/404 ,  G05B2219/41056

摘要： A positioning control apparatus has a moving body, a feed device having a guide mechanism for guiding the moving body in the direction of its feed axis and a drive mechanism for moving the moving body, a structural body supporting the feed device and a controller for controlling a moving position of the moving body with respect to a reference position on a machine tool by controlling the operation of the drive mechanism, and further has a calculating section calculating displacement of the feed device in the feed-axis direction with respect to the reference position caused by displacement of the structural body and a compensating section receiving the displacement data measured by the calculating section and adding modification data for eliminating the displacement to a control signal in the controller.

摘要翻译： 定位控制装置具有移动体，具有引导机构的进给装置，该引导机构用于沿着其进给轴线的方向引导移动体，以及用于使移动体移动的驱动机构，支撑进给装置的结构体和控制器 通过控制所述驱动机构的动作，使所述移动体相对于机床上的基准位置的移动位置，还具有计算部，计算所述进给装置相对于所述基准位置的进给轴方向的位移 由结构体的位移引起的补偿部分和接收由计算部分测量的位移数据的补偿部分，并将用于消除位移的修改数据添加到控制器中的控制信号。

公开(公告)号：US09094848B2

公开(公告)日：2015-07-28

申请号：US13816786

申请日：2010-08-23

申请人： Seigo Nakao ,  Koji Yamamoto

发明人： Seigo Nakao ,  Koji Yamamoto

IPC分类号： H04M3/00 ,  H04W24/02 ,  H04W72/04 ,  H04W72/08 ,  H04W52/24 ,  H04W16/32 ,  H04W52/14

CPC分类号： H04W24/02 ,  H04W16/32 ,  H04W52/143 ,  H04W52/244 ,  H04W72/0426 ,  H04W72/082

摘要： A base station apparatus, when performing the transmission controls of pico base stations, can perform an appropriate transmission control for each pico base station, while suppressing the increase of the amount of feedback information from a macro terminal to a macro base station and also suppressing the increase of the amount of transmission control information from the macro base station to the pico base station. In this apparatus, a transmission control unit (102) updates, on the basis of the control information, the priority level of each of a plurality of different correspondences in which the respective ones of transmission control guidelines are associated with the respective ones of a plurality of control information history patterns, and controls the transmissions on the basis of the control guidelines determined from the control information histories and the correspondences each having a respective higher priority level.

摘要翻译： 基站装置在执行微微基站的发送控制时，可以在抑制从宏终端到宏基站的反馈信息量的增加的同时，抑制各个微基站的发送控制， 传输控制信息量从宏基站增加到微微基站。 在该装置中，发送控制部（102）基于控制信息，更新各个发送控制指示与多个不同对应关系中的各个对应关系的优先级， 并且基于从控制信息历史确定的控制指南和每个具有相应较高优先级的对应来控制传输。

公开(公告)号：US08822229B2

公开(公告)日：2014-09-02

申请号：US13142262

申请日：2009-12-24

申请人： Shigeyuki Wakitani ,  Hiroshi Fujita ,  Takeshi Ishimaru ,  Koji Yamamoto ,  Yasuhiro Kurahashi ,  Junichi Onaya ,  Hiroyuki Masuda

发明人： Shigeyuki Wakitani ,  Hiroshi Fujita ,  Takeshi Ishimaru ,  Koji Yamamoto ,  Yasuhiro Kurahashi ,  Junichi Onaya ,  Hiroyuki Masuda

IPC分类号： G01N33/564

CPC分类号： G01N33/53 ,  G01N2400/40 ,  G01N2800/102

摘要： The inventions provides a method for immunologically determining a keratan sulfate level which method includes bringing an anti-keratan sulfate monoclonal antibody into contact with a biological sample, the anti-keratan sulfate monoclonal antibody exhibiting a relative reaction specificity between keratan sulfate-I and keratan sulfate-II represented by IC50KS-I/KS-II of 0.4 to 5, to thereby provide a signal; and detecting keratan sulfate contained in the biological sample from the signal. On the basis of the method, the invention also provides a joint disease detection method and a method for assessing the effect of a remedy for a joint disease and a candidate substance therefor. Through these methods, a very small amount of keratan sulfate contained in a sample, can be determined. Particularly, these methods can determine, at high-sensitivity and high-specificity, the total keratan sulfate including keratan sulfate-I, which have been difficult to determine through a conventional technique. The methods also enables detect a joint disease and assess the effect of a remedy for a joint disease or a candidate substance therefor.

摘要翻译： 本发明提供了一种免疫测定硫酸角质素水平的方法，该方法包括使硫酸角质素硫酸单克隆抗体与生物样品接触，硫酸角质素-I与硫酸角质素之间呈现相对反应特异性的硫酸角质素单体抗体 -II由IC50KS-I / KS-II表示，为0.4〜5，从而提供信号; 并从信号中检测生物样品中所含的硫酸角质素。 在该方法的基础上，本发明还提供了关于联合疾病的检测方法和评估对于关节疾病及其候选物质的补救效果的方法。 通过这些方法，可以测定样品中所含的极少量硫酸角质素。 特别地，这些方法可以高灵敏度和高特异性地确定通过常规技术难以确定的总硫酸角质素，包括硫酸角质素-I。 该方法还能够检测关节疾病并评估对于关节疾病或候选物质的补救的效果。