公开(公告)号：US06869829B2

公开(公告)日：2005-03-22

申请号：US10211308

申请日：2002-08-05

申请人： Junichi Hikita ,  Koji Yamamoto ,  Isamu Nishimura ,  Nobuhisa Kumamoto

发明人： Junichi Hikita ,  Koji Yamamoto ,  Isamu Nishimura ,  Nobuhisa Kumamoto

IPC分类号： H01L23/544 ,  H01L21/60

CPC分类号： H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15151 ,  Y10S438/975 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor chip (3) to be positioned with a front face thereof downward for formation of a chip-on-chip structure has electrode marks (35) provided on a back face (34) thereof. The electrode marks (35) are respectively provided in association with a plurality of electrodes (33) provided on the front face (31) of the semiconductor chip in the same arrangement as the arrangement of the electrodes (33). The arrangement of the electrode marks (35) represents the arrangement of the electrodes (33) on the front face (31) when viewed from the side of the back face (34) of the semiconductor chip 3. Therefore, the semiconductor chip (3) can easily be positioned with the front face downward on the basis of the electrode marks (35).

摘要翻译： 为了形成片上芯片结构，其前表面向下定位的半导体芯片（3）具有设置在其背面（34）上的电极标记（35）。 电极标记（35）与设置在半导体芯片的正面（31）上的多个电极（33）分别设置成与电极（33）的布置相同的布置。 电极标记（35）的布置表示从半导体芯片3的背面（34）的侧面观察时的正面（31）上的电极（33）的配置。因此，半导体芯片（3） ）可以根据电极标记（35）容易地将前表面向下定位。

公开(公告)号：US06476499B1

公开(公告)日：2002-11-05

申请号：US09499579

申请日：2000-02-07

申请人： Junichi Hikita ,  Koji Yamamoto ,  Isamu Nishimura ,  Nobuhisa Kumamoto

发明人： Junichi Hikita ,  Koji Yamamoto ,  Isamu Nishimura ,  Nobuhisa Kumamoto

IPC分类号： H01L2352

CPC分类号： H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15151 ,  Y10S438/975 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor chip (3) to be positioned with a front face thereof downward for formation of a chip-on-chip structure has electrode marks (35) provided on a back face (34) thereof. The electrode marks (35) are respectively provided in association with a plurality of electrodes (33) provided on the front face (31) of the semiconductor chip in the same arrangement as the arrangement of the electrodes (33). The arrangement of the electrode marks (35) represents the arrangement of the electrodes (33) on the front face (31) when viewed from the side of the back face (34) of the semiconductor chip 3. Therefore, the semiconductor chip (3) can easily be positioned with the front face downward on the basis of the electrode marks (35).

摘要翻译： 为了形成片上芯片结构，其前表面向下定位的半导体芯片（3）具有设置在其背面（34）上的电极标记（35）。 电极标记（35）与设置在半导体芯片的正面（31）上的多个电极（33）分别设置成与电极（33）的布置相同的布置。 电极标记（35）的布置表示从半导体芯片3的背面（34）的侧面观察时的正面（31）上的电极（33）的配置。因此，半导体芯片（3） ）可以根据电极标记（35）容易地将前表面向下定位。

公开(公告)号：US06404061B1

公开(公告)日：2002-06-11

申请号：US09512061

申请日：2000-02-24

申请人： Junichi Hikita ,  Isamu Nishimura ,  Nobuhisa Kumamoto ,  Yoshiyasu Morishima

发明人： Junichi Hikita ,  Isamu Nishimura ,  Nobuhisa Kumamoto ,  Yoshiyasu Morishima

IPC分类号： H01L2348

CPC分类号： H01L25/0657 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/00014

摘要： A semiconductor device having a solid device, and a semiconductor chip bonded to the solid device with a back face thereof being opposed to a front face of the solid device. The semiconductor chip has a back electrode provided on the back face thereof and electrically connected to an electrode provided on a front face thereof through a through-hole. The solid device may be a wiring board or another semiconductor chip. Further another semiconductor chip may be stacked and bonded onto the front face of the semiconductor chip.

摘要翻译： 具有固体器件的半导体器件和与固体器件接合的半导体芯片，其背面与固体器件的正面相对。 半导体芯片具有设置在其背面上的背电极，并且通过通孔与设置在其正面上的电极电连接。 固体器件可以是布线板或另一半导体芯片。 另外的另一半导体芯片可以堆叠并结合到半导体芯片的正面上。

公开(公告)号：US06897091B2

公开(公告)日：2005-05-24

申请号：US10145892

申请日：2002-05-16

申请人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Nobuhisa Kumamoto

发明人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Nobuhisa Kumamoto

IPC分类号： H01L21/301 ,  H01L21/60 ,  H01L23/485 ,  H01L23/50 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/44

CPC分类号： H01L25/0657 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2224/05669 ,  H01L2224/05099

摘要： A semiconductor device having a metal layer at the peripheral area surrounding an element forming area formed on a semiconductor substrate. This metal layer may be connected to the grounding potential or the power potential. The peripheral area is a scribing line area for example. The metal layer may be formed simultaneously with the formation of a bump within the element forming area.

摘要翻译： 一种在围绕形成在半导体衬底上的元件形成区域的周边区域具有金属层的半导体器件。 该金属层可以连接到接地电位或电源电位。 外围区域是例如划线区域。 金属层可以与在元件形成区域内形成凸块同时形成。

公开(公告)号：US07045900B2

公开(公告)日：2006-05-16

申请号：US10797018

申请日：2004-03-11

申请人： Junichi Hikita ,  Goro Nakatani ,  Nobuhisa Kumamoto ,  Katsumi Sameshima ,  Kazutaka Shibata ,  Shigeyuki Ueda

发明人： Junichi Hikita ,  Goro Nakatani ,  Nobuhisa Kumamoto ,  Katsumi Sameshima ,  Kazutaka Shibata ,  Shigeyuki Ueda

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/81 ,  H01L23/49575 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/28 ,  H01L24/31 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05669 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73207 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/85399 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/013

摘要： A semiconductor chip having a functional bump provided on a surface of a semiconductor substrate thereof for electrical connection between an internal circuit thereof and a solid device, and a dummy bump not serving for the electrical connection between the internal circuit and the solid device. The dummy bump may be a stress relieving bump for relieving stresses exerted thereon. The dummy bump may be connected to a low impedance portion. The functional bump and the dummy bump may be provided on a surface protective film. In this case, the dummy bump is provided on a recess formed in the surface protective film.

摘要翻译： 具有设置在其半导体衬底的表面上的用于在其内部电路和固体器件之间进行电连接的功能性凸块的半导体芯片和不用于内部电路和固体器件之间的电连接的虚拟凸起。 虚拟凸块可以是用于减轻施加在其上的应力的应力消除凸块。 虚拟凸块可以连接到低阻抗部分。 可以在表面保护膜上设置功能性凸块和虚设凸块。 在这种情况下，在形成在表面保护膜上的凹部上设置虚拟凸块。

公开(公告)号：US06724084B1

公开(公告)日：2004-04-20

申请号：US09499384

申请日：2000-02-07

申请人： Junichi Hikita ,  Goro Nakatani ,  Nobuhisa Kumamoto ,  Katsumi Sameshima ,  Kazutaka Shibata ,  Shigeyuki Ueda

发明人： Junichi Hikita ,  Goro Nakatani ,  Nobuhisa Kumamoto ,  Katsumi Sameshima ,  Kazutaka Shibata ,  Shigeyuki Ueda

IPC分类号： H01L2348

CPC分类号： H01L24/81 ,  H01L23/49575 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/28 ,  H01L24/31 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05669 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73207 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/85399 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/013

摘要： A semiconductor chip having a functional bump provided on a surface of a semiconductor substrate thereof for electrical connection between an internal circuit thereof and a solid device, and a dummy bump not serving for the electrical connection between the internal circuit and the solid device. The dummy bump may be a stress relieving bump for relieving stresses exerted thereon. The dummy bump may be connected to a low impedance portion. The functional bump and the dummy bump may be provided on a surface protective film. In this case, the dummy bump is provided on a recess formed in the surface protective film.

公开(公告)号：US06404040B1

公开(公告)日：2002-06-11

申请号：US09497157

申请日：2000-02-03

申请人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Nobuhisa Kumamoto

发明人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Nobuhisa Kumamoto

IPC分类号： H01L2358

CPC分类号： H01L25/0657 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2224/05669 ,  H01L2224/05099

摘要： A semiconductor device having a metal layer at the peripheral area surrounding an element forming area formed on a semiconductor substrate. This metal layer may be connected to the grounding potential or the power potential. The peripheral area is a scribing line area for example. The metal layer may be formed simultaneously with the formation of a bump within the element forming area.

摘要翻译： 一种在围绕形成在半导体衬底上的元件形成区域的周边区域具有金属层的半导体器件。 该金属层可以连接到接地电位或电源电位。 外围区域是例如划线区域。 金属层可以与在元件形成区域内形成凸块同时形成。

公开(公告)号：US06838312B2

公开(公告)日：2005-01-04

申请号：US10314289

申请日：2002-12-09

申请人： Junichi Hikita ,  Koji Yamamoto

发明人： Junichi Hikita ,  Koji Yamamoto

IPC分类号： H01L25/18 ,  H01L23/02 ,  H01L25/065 ,  H01L25/07 ,  H01L21/44

CPC分类号： H01L25/0655 ,  H01L2224/16225

摘要： A semiconductor device having a plurality of semiconductor chips respectively joined to predetermined positions on a surface of a solid, and a frame holding the plurality of semiconductor chips in a relative positional relationship corresponding to joint positions on the surface of the solid. The solid may be another semiconductor chip or a wiring board. The plurality of semiconductor chips may be bonded to a surface, opposite to the surface, of the solid, of the frame. The plurality of semiconductor chips may be respectively fitted in through holes formed in the frame.

公开(公告)号：US06717244B1

公开(公告)日：2004-04-06

申请号：US09511108

申请日：2000-02-23

申请人： Junichi Hikita ,  Koji Yamamoto

发明人： Junichi Hikita ,  Koji Yamamoto

IPC分类号： H01L2302

CPC分类号： H01L25/0655 ,  H01L2224/16225

摘要： A semiconductor device having a plurality of semiconductor chips respectively joined to predetermined positions on a surface of a solid, and a frame holding the plurality of semiconductor chips in a relative positional relationship corresponding to joint positions on the surface of the solid. The solid may be another semiconductor chip or a wiring board. The plurality of semiconductor chips may be bonded to a surface, opposite to the surface of the solid, of the frame. The plurality of semiconductor chips may be respectively fitted in through holes formed in the frame.

摘要翻译： 具有分别连接到固体表面上的预定位置的多个半导体芯片的半导体器件和以与固体表面上的接合位置相对应的相对位置关系保持多个半导体芯片的框架。 固体可以是另一种半导体芯片或布线板。 多个半导体芯片可以结合到框架的与固体的表面相对的表面。 多个半导体芯片可以分别安装在形成在框架中的通孔中。

公开(公告)号：US07307349B2

公开(公告)日：2007-12-11

申请号：US11150129

申请日：2005-06-13

申请人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Koji Yamamoto

发明人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Koji Yamamoto

IPC分类号： H01L23/52

CPC分类号： H01L24/13 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/17517 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013

摘要： A semiconductor device including a first semiconductor chip, a second semiconductor chip bonded to the first semiconductor chip in a stacked relation, and a registration structure which causes the first and second semiconductor chips to be positioned with respect to each other by depression-projection engagement therebetween. The registration structure includes, for example, a registration recess provided on a surface of the first semiconductor chip, and a registration projection provided on a surface of the second semiconductor chip for engagement with the registration recess. The registration projection may be a spherical member provided on the surface of the second semiconductor chip.

摘要翻译： 一种半导体器件，包括第一半导体芯片，以堆叠关系结合到第一半导体芯片的第二半导体芯片，以及配准结构，其使得第一半导体芯片和第二半导体芯片通过其间的凹凸突起相互相对于彼此定位 。 配准结构包括例如设置在第一半导体芯片的表面上的配准凹槽以及设置在第二半导体芯片的表面上用于与配准凹槽接合的配准突起。 配准突起可以是设置在第二半导体芯片的表面上的球形部件。