利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

21 条记录 (耗时 0.018 秒)

    Multiple narrow-line-channel fet having improved noise characteristics
    6.
    发明授权
    Multiple narrow-line-channel fet having improved noise characteristics 失效
    具有改善的噪声特性的多个窄线通道的胎儿

    公开(公告)号：US5726467A

    公开(公告)日：1998-03-10

    申请号：US954908

    申请日：1992-09-30

    申请人： Yoshikazu Nakagawa

    发明人： Yoshikazu Nakagawa

    IPC分类号： H01L21/265 ,  H01L21/338 ,  H01L29/10 ,  H01L29/812 ,  H01L31/0328 ,  H01L31/0336

    CPC分类号： H01L29/1029

    摘要： Insulating layers are formed, for instance, by ion injection, in a multilayer of compound semiconductor layers in regions spaced at predetermined intervals, to leave a plurality of narrow channel layers between the insulating layers. A gate electrode is formed on the insulating layers and channel layers so as to traverse those layers.

    摘要翻译： 绝缘层例如通过离子注入在以预定间隔隔开的区域中的多层化合物半导体层中形成，以在绝缘层之间留下多个窄通道层。 在绝缘层和沟道层上形成栅电极以便穿过这些层。

    Semiconductor device and manufacturing method therefor
    8.
    发明申请
    Semiconductor device and manufacturing method therefor 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20050051845A1

    公开(公告)日：2005-03-10

    申请号：US10910576

    申请日：2004-08-04

    申请人： Yoshikazu Nakagawa ,  Naoki Izumi

    发明人： Yoshikazu Nakagawa ,  Naoki Izumi

    IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

    CPC分类号： H01L21/823835 ,  H01L21/823842

    摘要： A gate electrode in an NMOS region is one of intrinsic silicon and a material having a work function equivalent to that of intrinsic silicon, and a material having a work function smaller than that of intrinsic silicon. A gate electrode in a PMOS region is one of intrinsic silicon and a material having a work function equivalent to that of intrinsic silicon, and a material having a work function larger than that of intrinsic silicon. Further, a source/drain region in the NMOS region includes a silicide layer of a material having a work function smaller than that of intrinsic silicon, and a source/drain region in the PMOS region includes a silicide layer of a material having a work function larger than that of intrinsic silicon.

    摘要翻译： NMOS区域中的栅电极是本征硅和具有与本征硅相同功函数的材料之一，以及功函数小于本征硅的功函数的材料。 PMOS区域中的栅电极是本征硅和具有与本征硅的功函数相当的功函数的材料之一，以及功函数大于本征硅的功函数的材料。 此外，NMOS区域中的源极/漏极区域包括具有比本征硅的功函数小的功函数的硅化物层，并且PMOS区中的源极/漏极区包括具有功函数的材料的硅化物层 大于本征硅。

    Compound semiconductor device
    9.
    发明授权
    Compound semiconductor device 失效
    复合半导体器件

    公开(公告)号：US5343056A

    公开(公告)日：1994-08-30

    申请号：US931042

    申请日：1992-08-17

    申请人： Yoshikazu Nakagawa

    发明人： Yoshikazu Nakagawa

    IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/08 ,  H01L29/36 ,  H01L29/778 ,  H01L29/205 ,  H01L29/161 ,  H01L29/80

    CPC分类号： H01L29/0891 ,  H01L29/365 ,  H01L29/7787

    摘要： A compound semiconductor device includes an undoped semiconductor layer; a doped semiconductor layer formed on the undoped semiconductor layer and having smaller electron affinity than the undoped semiconductor layer, impurities being doped in the doped semiconductor layer; a gate electrode formed on the doped semiconductor layer; and a source electrode and a drain electrode respectively formed at both sides of the gate electrode, wherein an impurity concentration of the doped semiconductor layer is selected such that a portion of the doped semiconductor layer located immediately below the gate electrode is not completely depleted in a state in which a gate voltage is not applied to the gate electrode, and is completely depleted in a state in which a negative voltage for minimizing a noise figure is applied to the gate electrode.

    摘要翻译： 化合物半导体器件包括未掺杂的半导体层; 形成在未掺杂的半导体层上并且具有比未掺杂的半导体层更小的电子亲和力的掺杂半导体层，掺杂半导体层中的杂质; 形成在所述掺杂半导体层上的栅电极; 以及分别形成在栅电极的两侧的源电极和漏电极，其中选择掺杂半导体层的杂质浓度，使得位于栅电极正下方的掺杂半导体层的一部分未完全耗尽 栅极电压不施加到栅电极的状态，并且在用于使噪声系数最小化的负电压施加到栅电极的状态下完全耗尽。

    High electron mobility transistor
    10.
    发明授权
    High electron mobility transistor 失效
    高电子迁移率晶体管

    公开(公告)号：US5321278A

    公开(公告)日：1994-06-14

    申请号：US894780

    申请日：1992-06-05

    申请人： Yoshikazu Nakagawa

    发明人： Yoshikazu Nakagawa

    IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/778 ,  H01L29/06 ,  H01L31/072 ,  H01L31/109

    CPC分类号： H01L29/7787

    摘要： A field-effect transistor (FET) in which an InGaAs layer formed on a GaAs substrate is formed in such a manner that the In composition ratio on the gate electrode side on the substrate surface is made small and the In composition ratio on the GaAs substrate side is made large. Thereby, the FET does not cause a decline in the mutual conductance in the FET and a decline in the noise figure (NF) even if negative voltage is applied to a gate electrode.

    摘要翻译： 形成在GaAs衬底上形成的InGaAs层的场效应晶体管（FET）以使得衬底表面上的栅电极侧的In组成比变小并且GaAs衬底上的In组成比 一边做得很大。 因此，即使负电压施加到栅电极，FET也不会导致FET中的互导性的下降和噪声系数（NF）的下降。