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    REDUCED SOFT ERROR RATE THROUGH METAL FILL AND PLACEMENT
    1.
    发明申请
    REDUCED SOFT ERROR RATE THROUGH METAL FILL AND PLACEMENT 有权
    通过金属填充和放置减少软错误率

    公开(公告)号：US20100301463A1

    公开(公告)日：2010-12-02

    申请号：US12473435

    申请日：2009-05-28

    申请人： K. Paul Muller ,  Alicia Wang

    发明人： K. Paul Muller ,  Alicia Wang

    IPC分类号： H01L23/556 ,  H01L21/71

    CPC分类号： H01L23/556 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for reducing single event upsets in an integrated circuit includes the step of providing a plurality of levels within the integrated circuit, wherein the plurality of levels within the integrated circuit are in a stacked arrangement. The method also includes the step of providing a plurality of metal fill patterns within each of the plurality of levels within the integrated circuit. The method further includes the step of placing the plurality of metal fill patterns within at least one of the plurality of levels in a pattern such that a line of sight towards an active silicon layer does not exist within the stacked arrangement of the plurality of levels, thereby increasingly absorbing ionizing radiation particles, and thereby reducing single event upsets in the integrated circuit.

    摘要翻译： 一种用于减少集成电路中的单事件扰乱的方法包括在集成电路内提供多个电平的步骤，其中集成电路内的多个电平处于堆叠布置。 该方法还包括在集成电路内的多个电平的每一个内提供多个金属填充图案的步骤。 该方法还包括将多个金属填充图案放置在多个层中的至少一个层中的图案的步骤，使得朝向有源硅层的视线不存在于多个层次的堆叠布置中， 从而越来越多地吸收电离辐射颗粒，从而减少集成电路中的单个事件的不适。

    Reduced soft error rate through metal fill and placement
    2.
    发明授权
    Reduced soft error rate through metal fill and placement 有权
    通过金属填充和放置降低软错误率

    公开(公告)号：US08102033B2

    公开(公告)日：2012-01-24

    申请号：US12473435

    申请日：2009-05-28

    申请人： K. Paul Muller ,  Alicia Wang

    发明人： K. Paul Muller ,  Alicia Wang

    IPC分类号： H01L23/556

    CPC分类号： H01L23/556 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for reducing single event upsets in an integrated circuit includes the step of providing a plurality of levels within the integrated circuit, wherein the plurality of levels within the integrated circuit are in a stacked arrangement. The method also includes the step of providing a plurality of metal fill patterns within each of the plurality of levels within the integrated circuit. The method further includes the step of placing the plurality of metal fill patterns within at least one of the plurality of levels in a pattern such that a line of sight towards an active silicon layer does not exist within the stacked arrangement of the plurality of levels, thereby increasingly absorbing ionizing radiation particles, and thereby reducing single event upsets in the integrated circuit.

    摘要翻译： 一种用于减少集成电路中的单事件扰乱的方法包括在集成电路内提供多个电平的步骤，其中集成电路内的多个电平处于堆叠布置。 该方法还包括在集成电路内的多个电平的每一个内提供多个金属填充图案的步骤。 该方法还包括将多个金属填充图案放置在多个层中的至少一个层中的图案的步骤，使得朝向有源硅层的视线不存在于多个层次的堆叠布置中， 从而越来越多地吸收电离辐射颗粒，从而减少集成电路中的单个事件的不适。

    In-line stacking of transistors for soft error rate hardening
    3.
    发明授权
    In-line stacking of transistors for soft error rate hardening 有权
    用于软错误率硬化的晶体管的在线堆叠

    公开(公告)号：US09165917B2

    公开(公告)日：2015-10-20

    申请号：US12473409

    申请日：2009-05-28

    申请人： Ethan H. Cannon ,  David F. Heidel ,  K. Paul Muller ,  Alicia Wang

    发明人： Ethan H. Cannon ,  David F. Heidel ,  K. Paul Muller ,  Alicia Wang

    IPC分类号： H01L27/11 ,  H01L27/02 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L27/0207 ,  H01L21/823871 ,  H01L27/092

    摘要： Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of “in-line” connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art “side-by-side” transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.

    摘要翻译： 一对CMOS晶体管中的每一个形成在其自身的岛中，并且每个晶体管的栅极端子由连接两个栅极端子的单个直列导体形成。 与现有技术的“并排”晶体管堆叠通过使用相比，这种“在线”连接实现了与电离辐射颗粒同时撞击两个晶体管的能力的降低近乎五次的改进 具有跨越两个晶体管的相对较小的立体角。 这导致了晶体管的“硬化”，并提高了它们对单一事件的影响，从而提高了晶体管的软错误率（SER）。

    IN-LINE STACKING OF TRANSISTORS FOR SOFT ERROR RATE HARDENING
    4.
    发明申请
    IN-LINE STACKING OF TRANSISTORS FOR SOFT ERROR RATE HARDENING 有权
    用于软错误速率硬化的晶体管的在线堆叠

    公开(公告)号：US20100301446A1

    公开(公告)日：2010-12-02

    申请号：US12473409

    申请日：2009-05-28

    申请人： Ethan H. Cannon ,  David F. Heidel ,  K. Paul Muller ,  Alicia Wang

    发明人： Ethan H. Cannon ,  David F. Heidel ,  K. Paul Muller ,  Alicia Wang

    IPC分类号： H01L27/12 ,  H01L21/28

    CPC分类号： H01L27/0207 ,  H01L21/823871 ,  H01L27/092

    摘要： Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of “in-line” connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art “side-by-side” transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.

    摘要翻译： 一对CMOS晶体管中的每一个形成在其自身的岛中，并且每个晶体管的栅极端子由连接两个栅极端子的单个直列导体形成。 与现有技术的“并排”晶体管堆叠通过使用相比，这种“在线”连接实现了与电离辐射颗粒同时撞击两个晶体管的能力的降低近乎五次的改进 具有跨越两个晶体管的相对较小的立体角。 这导致了晶体管的“硬化”，并提高了它们对单一事件的影响，从而提高了晶体管的软错误率（SER）。

    Alignment insensitive D-cache cell
    7.
    发明授权
    Alignment insensitive D-cache cell 有权
    对齐不敏感的D缓存单元

    公开(公告)号：US07304352B2

    公开(公告)日：2007-12-04

    申请号：US11111454

    申请日：2005-04-21

    申请人： K. Paul Muller ,  Kevin A. Batson ,  Michael J. Lee

    发明人： K. Paul Muller ,  Kevin A. Batson ,  Michael J. Lee

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

    摘要： A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one read port on a true side and one on the complement side. Asymmetry is additionally minimized in layout as cross coupling on both the true and complement sides rises up one level by providing from the local interconnect level a via connection to a M1 or metallization level. Moreover, the distance between the local interconnect (MC) and the gate conductor structure (PC) has been enlarged and equalized for each of the pFETs in the cross-latched SRAM cell. As a result, the SRAM cell has been rendered insensitive to overlay (local interconnect processing too close) by maximizing this MC-PC distance.

    摘要翻译： 具有改进的示意图和布局设计的D缓存SRAM单元，其显示出来自电路原理图和物理单元布局视角的增加的对称性。 也就是说，SRAM单元包括两个读取端口，并且通过在真实侧提供一个读取端口和在补充端上提供一个读取端口来最小化不对称性。 通过从本地互连级别提供通向M1或金属化级别的通孔连接，通过从真实和补偿侧两者的交叉耦合上升到一个级别，不对称性在布局中另外最小化。 此外，局部互连（MC）和栅极导体结构（PC）之间的距离已经在交叉锁存SRAM单元中的每个pFET被放大和均衡。 因此，通过最大化这个MC-PC距离，SRAM单元已经对覆盖（局部互连处理太近）变得不敏感。

    Double gated vertical transistor with different first and second gate materials
    8.
    发明授权
    Double gated vertical transistor with different first and second gate materials 失效
    双门控垂直晶体管，具有不同的第一和第二栅极材料

    公开(公告)号：US06960806B2

    公开(公告)日：2005-11-01

    申请号：US09886823

    申请日：2001-06-21

    申请人： Andres Bryant ,  Meikei Ieong ,  K. Paul Muller ,  Edward J. Nowak ,  David M. Fried ,  Jed Rankin

    发明人： Andres Bryant ,  Meikei Ieong ,  K. Paul Muller ,  Edward J. Nowak ,  David M. Fried ,  Jed Rankin

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76

    CPC分类号： H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

    摘要： Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.

    摘要翻译： 因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。 本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。 通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。 特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。 例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

    Method and apparatus for overlay measurement
    9.
    发明授权
    Method and apparatus for overlay measurement 失效
    覆盖测量方法和装置

    公开(公告)号：US06463184B1

    公开(公告)日：2002-10-08

    申请号：US09335091

    申请日：1999-06-17

    申请人： Chris Gould ,  K. Paul Muller ,  V. C. Jai Prakash ,  Robert van den Berg

    发明人： Chris Gould ,  K. Paul Muller ,  V. C. Jai Prakash ,  Robert van den Berg

    IPC分类号： G06K936

    CPC分类号： G03F9/7092 ,  G03F7/70633

    摘要： A process for measuring the alignment of different layers on a semiconductor wafer (33) includes forming repetitive alignment marks (14, 24) having substantially the same period on the different layers on the wafer (33). The images of the overlay alignment marks (14, 24) are converted from space domain to frequency domain through Fourier transformations. The alignment measurements are performed by calculating the phase difference between the images corresponding to the repetitive patterns (14, 24) on different layers.

    摘要翻译： 用于测量半导体晶片（33）上的不同层的对准的方法包括在晶片（33）上的不同层上形成具有基本上相同周期的重复对准标记（14,24）。 覆盖对齐标记（14,24）的图像通过傅立叶变换从空间域转换到频域。 通过计算对应于不同层上的重复图案（14,24）的图像之间的相位差来执行对准测量。

    Modular refrigeration unit health monitoring
    10.
    发明授权
    Modular refrigeration unit health monitoring 有权
    模块化制冷机组健康监测

    公开(公告)号：US09053223B2

    公开(公告)日：2015-06-09

    申请号：US13355063

    申请日：2012-01-20

    申请人： Scott Hadderman ,  Timothy R. Marchini ,  K. Paul Muller ,  Katie L. Pizzolato ,  Andrew H. Vogel

    发明人： Scott Hadderman ,  Timothy R. Marchini ,  K. Paul Muller ,  Katie L. Pizzolato ,  Andrew H. Vogel

    IPC分类号： G21C17/00 ,  G06F15/00 ,  G06F11/34 ,  G06F11/30

    CPC分类号： G06F11/3476 ,  F25B49/005 ,  G06F1/206 ,  G06F11/3058 ,  G06F11/3072

    摘要： A method for modular refrigeration unit (MRU) health monitoring includes receiving log data on a log data input from the MRU by a MRU health monitor, the log data comprising a plurality of datapoints, each of the plurality of datapoints comprising a position of a control valve of the MRU and a corresponding time; determining by the MRU health monitor a plurality of MRU parameters from the log data; determining a plurality of MRU health flags based on the MRU parameters; adding the plurality of MRU health flags to determine an MRU health score; determining whether the MRU health score is higher than a replacement threshold; and indicating replacement of the MRU in the event the MRU health score is higher than the replacement threshold.

    摘要翻译： 一种用于模块化制冷单元（MRU）健康监测的方法包括：通过MRU健康监视器接收来自MRU的日志数据的日志数据，所述日志数据包括多个数据点，所述多个数据点中的每一个包括控制的位置 MRU的阀门和相应的时间; 由MRU健康监视器根据对数数据确定多个MRU参数; 基于MRU参数确定多个MRU健康标志; 添加多个MRU健康标志以确定MRU健康评分; 确定MRU健康评分是否高于置换阈值; 并且在MRU健康评分高于替换阈值的情况下指示MRU的替换。