公开(公告)号：US11762594B2

公开(公告)日：2023-09-19

申请号：US17469486

申请日：2021-09-08

Applicant: Kioxia Corporation

Inventor： Naoki Kimura ,  Junya Kishikawa

IPC: G06F13/16 ,  G06F13/42 ,  G06F3/06 ,  G06F1/10 ,  G06F13/40 ,  G11C5/14

CPC classification number: G06F3/0659 ,  G06F1/10 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2213/0026 ,  G06F2213/0034 ,  G11C5/14

Abstract: A memory system of an embodiment is connectable to a host and includes a nonvolatile memory and a memory controller. The memory controller includes: a signal line which transfers a signal sent from the host; a resistance element disposed between and electrically connected to the signal line and a wiring line given a reference potential of the memory system; a switching element connected serially to the resistance element and capable of switching a connection between the signal line and the wiring line; and a control circuit which controls the switching element to switch the connection between the signal line and the wiring line from a connected state to a disconnected state, when a change from a first potential to a second potential occurs on the signal line or when a change from the second potential to the first potential occurs on the signal line.

公开(公告)号：US12166320B2

公开(公告)日：2024-12-10

申请号：US17472382

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Kazuyuki Matsuzaki ,  Naoki Kimura

IPC: H01R25/00 ,  H01R12/70 ,  H01R12/73 ,  H05K1/14 ,  H05K7/20

Abstract: According to one embodiment, a storage system includes a circuit board, a connector, a first memory system, and a second memory system. The connector is on the circuit board and includes first and second slots, the first slot having a first terminal group of first terminals aligned in a first direction, and the second slot being separated from the first slot in a second direction not parallel with the first direction and having a second terminal group of second terminals aligned in the first direction. The first terminal group is reverse to the second terminal group in terminal arrangement order in the first direction. The first memory system is connectable to the first terminal group, while the first memory system is inserted into the first slot. The second memory system is connectable to the second terminal group, while the second memory system is inserted into the second slot.

公开(公告)号：US12165713B2

公开(公告)日：2024-12-10

申请号：US17896828

申请日：2022-08-26

Applicant: Kioxia Corporation

Inventor： Naoki Kimura

IPC: G11C16/30 ,  G06F13/16 ,  G11C5/14 ,  G11C16/04 ,  G06F3/06 ,  G06F13/14 ,  G06F13/42 ,  G11C11/4072 ,  G11C11/4074

Abstract: A memory system includes: a connector including a first terminal and a second terminal, each of which is capable of being connected to a host device; a non-volatile memory; and a controller connected between the connector and the non-volatile memory. The controller includes: a control circuit including a first node and a second node; a first signal line connected between the first terminal and the first node and capable of being pulled up to a first power level or a second power level; a second signal line connected to the second terminal; and a first resistance element including one end connected to the first signal line and the other end connected to the second signal line.

公开(公告)号：US12094866B2

公开(公告)日：2024-09-17

申请号：US18203693

申请日：2023-05-31

Applicant: Kioxia Corporation

Inventor： Hayato Masubuchi ,  Naoki Kimura ,  Manabu Matsumoto ,  Toyota Morimoto

IPC: G11C5/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/528 ,  H01L23/552 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H05K1/02 ,  H05K1/18 ,  H05K3/30 ,  H10B69/00

CPC classification number: H01L25/18 ,  G11C5/02 ,  H01L23/3142 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H05K1/0225 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/181 ,  H05K3/305 ,  H10B69/00 ,  H01L23/3121 ,  H01L2924/0002 ,  H05K2201/09136 ,  H05K2201/09681 ,  H05K2201/10159 ,  Y02P70/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

公开(公告)号：US11258195B2

公开(公告)日：2022-02-22

申请号：US16567174

申请日：2019-09-11

Applicant: Kioxia Corporation

Inventor： Naoki Kimura

IPC: H01R24/00 ,  H01R12/72 ,  H01R12/70 ,  H05K1/11 ,  H05K5/00 ,  G06F3/06

Abstract: According to one embodiment, a storage device is disclosed. The storage device includes a substrate, a first connector provided on the substrate and including a notch, and a nonvolatile memory provided on the substrate. The storage device further includes a first conductive part provided on the first connector and being adjacent to the notch.

公开(公告)号：US12154649B2

公开(公告)日：2024-11-26

申请号：US18347517

申请日：2023-07-05

Applicant: KIOXIA CORPORATION

Inventor： Masato Sugita ,  Naoki Kimura ,  Daisuke Kimura

IPC: G11C5/02 ,  G06F13/42 ,  G06F16/9535 ,  G11C5/04 ,  G11C5/06 ,  G11C14/00 ,  G11C16/04

Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

公开(公告)号：US11735230B2

公开(公告)日：2023-08-22

申请号：US17565713

申请日：2021-12-30

Applicant: Kioxia Corporation

Inventor： Masato Sugita ,  Naoki Kimura ,  Daisuke Kimura

IPC: G11C5/00 ,  G11C5/04 ,  G06F16/9535 ,  G11C5/06 ,  G11C5/02 ,  G11C16/04 ,  G11C14/00 ,  G06F13/42

CPC classification number: G11C5/04 ,  G06F13/4282 ,  G06F16/9535 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  G11C14/0018 ,  G11C16/04 ,  G06F2213/0032

Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

公开(公告)号：US11252817B1

公开(公告)日：2022-02-15

申请号：US17184504

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Naoki Kimura ,  Hiroaki Komaki

IPC: H05K1/02 ,  H05K1/11

Abstract: A printed wiring board includes first, second, and third wiring layers, first and second insulating members, and first and second vias. The first wiring layer includes a recognition mark and a first wiring on a first surface. The second wiring layer includes a first pad and a second wiring. The third wiring layer includes a third wiring. The first via penetrates the first insulating member and electrically connects the recognition mark to the first pad. The second via penetrates the second insulating member and electrically connects the first pad to the third wiring. The first pad and the first and second vias are in a region within an outer perimeter of the recognition mark when viewed from a direction orthogonal to the first surface.

公开(公告)号：US11914544B2

公开(公告)日：2024-02-27

申请号：US17841390

申请日：2022-06-15

Applicant: Kioxia Corporation

Inventor： Nana Kawamoto ,  Naoki Kimura

IPC: G06F13/42 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/1668 ,  G06F13/409

Abstract: According to one embodiment, a memory system includes a board, a memory controller, and a semiconductor memory. When a signal input to a third port or a command received from an outside of the memory system satisfies a first condition, the memory controller is configured to use a first port as a first signal port and to use a second port as a second signal port. When the signal input to the third port or the command received from the outside of the memory system satisfies a second condition, the memory controller is configured to use the first port as the second signal port and to use the second port as the first signal port.

公开(公告)号：US11710526B2

公开(公告)日：2023-07-25

申请号：US17578244

申请日：2022-01-18

Applicant: KIOXIA CORPORATION

Inventor： Naoki Kimura

IPC: G01R19/165 ,  G11C16/30 ,  H02H3/20 ,  G11C5/14 ,  G06F1/30

CPC classification number: G11C16/30 ,  G01R19/165 ,  G01R19/16533 ,  G06F1/30 ,  G11C5/143 ,  H02H3/20

Abstract: A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.