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9 条记录 (耗时 0.014 秒)

    Printed wiring board and memory system
    5.
    发明授权
    Printed wiring board and memory system 有权

    公开(公告)号：US11252817B1

    公开(公告)日：2022-02-15

    申请号：US17184504

    申请日：2021-02-24

    申请人： KIOXIA CORPORATION

    发明人： Naoki Kimura ,  Hiroaki Komaki

    IPC分类号： H05K1/02 ,  H05K1/11

    摘要： A printed wiring board includes first, second, and third wiring layers, first and second insulating members, and first and second vias. The first wiring layer includes a recognition mark and a first wiring on a first surface. The second wiring layer includes a first pad and a second wiring. The third wiring layer includes a third wiring. The first via penetrates the first insulating member and electrically connects the recognition mark to the first pad. The second via penetrates the second insulating member and electrically connects the first pad to the third wiring. The first pad and the first and second vias are in a region within an outer perimeter of the recognition mark when viewed from a direction orthogonal to the first surface.

    Memory system, method of controlling memory system, and host system
    6.
    发明授权
    Memory system, method of controlling memory system, and host system 有权

    公开(公告)号：US11914544B2

    公开(公告)日：2024-02-27

    申请号：US17841390

    申请日：2022-06-15

    申请人： Kioxia Corporation

    发明人： Nana Kawamoto ,  Naoki Kimura

    IPC分类号： G06F13/42 ,  G06F13/16 ,  G06F13/40

    CPC分类号： G06F13/4221 ,  G06F13/1668 ,  G06F13/409

    摘要： According to one embodiment, a memory system includes a board, a memory controller, and a semiconductor memory. When a signal input to a third port or a command received from an outside of the memory system satisfies a first condition, the memory controller is configured to use a first port as a first signal port and to use a second port as a second signal port. When the signal input to the third port or the command received from the outside of the memory system satisfies a second condition, the memory controller is configured to use the first port as the second signal port and to use the second port as the first signal port.

    Memory system
    7.
    发明授权
    Memory system 有权

    公开(公告)号：US11710526B2

    公开(公告)日：2023-07-25

    申请号：US17578244

    申请日：2022-01-18

    申请人： KIOXIA CORPORATION

    发明人： Naoki Kimura

    IPC分类号： G01R19/165 ,  G11C16/30 ,  H02H3/20 ,  G11C5/14 ,  G06F1/30

    CPC分类号： G11C16/30 ,  G01R19/165 ,  G01R19/16533 ,  G06F1/30 ,  G11C5/143 ,  H02H3/20

    摘要： A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11244708B2

    公开(公告)日：2022-02-08

    申请号：US17077560

    申请日：2020-10-22

    申请人： Kioxia Corporation

    发明人： Masato Sugita ,  Naoki Kimura ,  Daisuke Kimura

    IPC分类号： G11C5/06 ,  G11C5/04 ,  G06F16/9535 ,  G11C5/02 ,  G11C16/04 ,  G11C14/00 ,  G06F13/42

    摘要： According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.