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    Method for measuring withstand voltage of semiconductor epitaxial wafer and semiconductor epitaxial wafer
    1.
    发明申请
    Method for measuring withstand voltage of semiconductor epitaxial wafer and semiconductor epitaxial wafer 有权
    用于测量半导体外延晶片和半导体外延晶片的耐受电压的方法

    公开(公告)号：US20050118736A1

    公开(公告)日：2005-06-02

    申请号：US10484001

    申请日：2003-01-23

    申请人： Katsushi Akita ,  Masashi Yamashita ,  Makoto Kiyama

    发明人： Katsushi Akita ,  Masashi Yamashita ,  Makoto Kiyama

    IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L23/544 ,  H01L29/745 ,  H01L29/76

    CPC分类号： H01L22/14 ,  H01L22/34

    摘要： A measurement-facilitating method of measuring the breakdown voltage of a semiconductor epitaxial wafer, and a semiconductor epitaxial wafer whose breakdown voltage is superior are realized. In a method of measuring the breakdown voltage of a semiconductor epitaxial wafer having to do with the present invention, the breakdown voltage between contacts 12, 12 is measured only through the Schottky contacts, without need for ohmic contacts. Inasmuch as the manufacturing process of forming ohmic contacts is accordingly omitted, the semiconductor epitaxial wafer 10 may be readily used in a breakdown-voltage measurement test. The measurement of the wafer 10 breakdown voltage thus may be readily carried out. Likewise, because the inter-contact breakdown voltage V2 of a wafer 10 can be measured prior to manufacturing a working device from it, unsuitable wafers 10 can be excluded before they are cycled through the working-device fabrication process. Reduction in losses can accordingly be counted upon, in contrast to conventional measuring methods, by which inter-contact breakdown voltage V2 is measured following fabrication of the working devices.

    摘要翻译： 实现了测量半导体外延晶片的击穿电压的测量方法和击穿电压优良的半导体外延晶片。 在测量与本发明有关的半导体外延晶片的击穿电压的方法中，仅通过肖特基触点测量触点12,12之间的击穿电压，而不需要欧姆接触。 因此省略了形成欧姆接触的制造工艺，因此半导体外延晶片10可以容易地用于击穿电压测量测试。 因此，可以容易地进行晶片10的击穿电压的测量。 同样，由于可以在从其制造工作装置之前测量晶片10的接触间击穿电压V 2 2，所以不适合的晶片10可以在它们循环通过工作装置制造之前被排除 处理。 因此，与传统的测量方法相比，可以减少损耗，通过这些测量方法，在工作装置制造之后测量接触间击穿电压V 2 2。

    Method for measuring withstand voltage of semiconductor epitaxial wafer and semiconductor epitaxial wafer
    2.
    发明授权
    Method for measuring withstand voltage of semiconductor epitaxial wafer and semiconductor epitaxial wafer 有权
    用于测量半导体外延晶片和半导体外延晶片的耐受电压的方法

    公开(公告)号：US07195937B2

    公开(公告)日：2007-03-27

    申请号：US10484001

    申请日：2003-01-23

    申请人： Katsushi Akita ,  Masashi Yamashita ,  Makoto Kiyama

    发明人： Katsushi Akita ,  Masashi Yamashita ,  Makoto Kiyama

    IPC分类号： H01L21/66 ,  G01R31/26 ,  G01N27/02

    CPC分类号： H01L22/14 ,  H01L22/34

    摘要： A measurement-facilitating method of measuring the breakdown voltage of a semiconductor epitaxial wafer, and a semiconductor epitaxial wafer whose breakdown voltage is superior are realized. In a method of measuring the breakdown voltage of a semiconductor epitaxial wafer having to do with the present invention, the breakdown voltage between contacts 14 and 18 is measured only through the Schottky contacts, without need for ohmic contacts. Inasmuch as the manufacturing process of forming ohmic contacts is accordingly omitted, the semiconductor epitaxial wafer 10 may be readily used in a breakdown-voltage measurement test. The measurement of the wafer-10 breakdown voltage thus may be readily carried out. Likewise, because the inter-contact breakdown voltage V2 of a wafer 10 can be measured prior to manufacturing a working device from it, unsuitable wafers 10 can be excluded before they are cycled through the working-device fabrication process. Reduction in losses can accordingly be counted upon, in contrast to conventional measuring methods, by which inter-contact breakdown voltage V2 is measured following fabrication of the working devices.

    摘要翻译： 实现了测量半导体外延晶片的击穿电压的测量方法和击穿电压优良的半导体外延晶片。 在测量与本发明有关的半导体外延晶片的击穿电压的方法中，触点14和18之间的击穿电压仅通过肖特基触点测量，而不需要欧姆接触。 因此省略了形成欧姆接触的制造工艺，因此半导体外延晶片10可以容易地用于击穿电压测量测试。 因此，可以容易地进行晶片-10击穿电压的测量。 同样，由于可以在从其制造工作装置之前测量晶片10的接触间击穿电压V 2 2，所以不适合的晶片10可以在它们循环通过工作装置制造之前被排除 处理。 因此，与传统的测量方法相比，可以减少损耗，通过这些测量方法，在工作装置制造之后测量接触间击穿电压V 2 2。

    Method and device for determining backgate characteristics
    9.
    发明授权
    Method and device for determining backgate characteristics 失效
    用于确定背盖特性的方法和装置

    公开(公告)号：US06756607B2

    公开(公告)日：2004-06-29

    申请号：US10249710

    申请日：2003-05-01

    申请人： Masashi Yamashita ,  Mitsutaka Tsubokura ,  Makoto Kiyama

    发明人： Masashi Yamashita ,  Mitsutaka Tsubokura ,  Makoto Kiyama

    IPC分类号： H01L2358

    CPC分类号： H01L22/14

    摘要： Backgate-characteristics determination method and device that make for curtailing the fabrication of semiconductor circuit elements having defective backgate-characteristics. Initially a first C-V curve 30 representing the relation between a voltage applied to the obverse face of a wafer 20 serving as a substrate for semiconductor circuit elements, and its capacitance, is found. Next, a second C-V curve 32 is found through applying a voltage to the reverse face of the wafer 20. The backgate characteristics for the semiconductor circuit elements are determined based on a voltage-shift amount 34 for the wafer 20, found from the first C-V curve 30 and the second C-V curve 32.

    摘要翻译： 背栅特性确定方法和装置，其用于抑制具有缺陷背栅特性的半导体电路元件的制造。 首先，找到表示施加到用作半导体电路元件的基板的晶片20的正面的电压与其电容之间的关系的第一C-V曲线30。 接下来，通过向晶片20的反面施加电压来发现第二CV曲线32.半导体电路元件的背栅特性基于从第一CV找到的晶片20的电压移位量34来确定 曲线30和第二CV曲线32。

    Semiconductor device and method for producing the same
    10.
    发明授权
    Semiconductor device and method for producing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08890239B2

    公开(公告)日：2014-11-18

    申请号：US13884221

    申请日：2011-07-26

    申请人： Seiji Yaegashi ,  Makoto Kiyama ,  Mitsunori Yokoyama ,  Kazutaka Inoue ,  Masaya Okada ,  Yu Saitoh

    发明人： Seiji Yaegashi ,  Makoto Kiyama ,  Mitsunori Yokoyama ,  Kazutaka Inoue ,  Masaya Okada ,  Yu Saitoh

    IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/20

    CPC分类号： H01L29/7802 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/66712 ,  H01L29/7788 ,  H01L29/7789

    摘要： In a vertical semiconductor device including a channel in an opening, a semiconductor device whose high-frequency characteristics can be improved and a method for producing the semiconductor device are provided. The semiconductor device includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. An opening 28 extends from a top layer and reaches the n-type GaN-based drift layer. The semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, a drain electrode D, and a gate electrode G located on the regrown layer. Assuming that the source electrode serving as one electrode and the drain electrode serving as the other electrode constitute a capacitor, the semiconductor device includes a capacitance-decreasing structure that decreases the capacitance of the capacitor.

    摘要翻译： 在包括开口中的沟道的垂直半导体器件中，提供了可以提高其高频特性的半导体器件和制造半导体器件的方法。 半导体器件包括n型GaN基漂移层4 / p型GaN基阻挡层6 / n型GaN基接触层7.开口28从顶层延伸并到达n型GaN- 基漂移层。 半导体器件包括以覆盖开口的方式定位的再生长层27，包括电子漂移层22和电子供给层26的再生长层27，源电极S，漏电极D和位于 再生长层。 假设用作一个电极的源极和用作另一个电极的漏电极构成电容器，则半导体器件包括降低电容器的电容的电容减小结构。