公开(公告)号：US07518233B1

公开(公告)日：2009-04-14

申请号：US09590897

申请日：2000-06-09

申请人： Kouichi Takahashi ,  Kenichi Kasai ,  Takahiro Daikoku ,  Takayuki Uda ,  Toshitada Netsu ,  Takeshi Yamaguchi ,  Takahiko Matsushita ,  Osamu Maruyama

发明人： Kouichi Takahashi ,  Kenichi Kasai ,  Takahiro Daikoku ,  Takayuki Uda ,  Toshitada Netsu ,  Takeshi Yamaguchi ,  Takahiko Matsushita ,  Osamu Maruyama

IPC分类号： H01L23/12 ,  H01L23/10 ,  H01L23/34 ,  H01L23/28 ,  H01L21/00

CPC分类号： H01L23/4006 ,  H01L2023/4068 ,  H01L2023/4081 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/09701

摘要： A sealing structure for multi-chip modules stable in cooling performance and excelling in sealing reliability is to be provided. The under face of a frame 5 compatible with a wiring board 1 in thermal expansion rate is fixed with solder 8 to the face of the wiring board 1 for mounting semiconductor devices 2; a rubber O-ring 15 is placed between the upper face of the frame 5 and the under face of the circumference of an air-cooled: heat sink 7; the plastic member 6 making possible relative sliding is placed between the upper face of the circumference of the heat sink 7 and the upper frame 10; the upper face of a plastic member 6 is restrained with the inside middle stage of an upper frame 10; and the lower part of the upper frame 10 and the frame 5 are fastened together with bolts 9.

摘要翻译： 提供一种用于具有稳定的冷却性能和优异的密封可靠性的多芯片模块的密封结构。 以热膨胀率与布线板1相容的框架5的底面用焊料8固定到布线板1的面上，用于安装半导体器件2; 橡胶O形环15放置在框架5的上表面和空气冷却：散热器7的圆周的下表面之间; 能够进行相对滑动的塑料构件6设置在散热器7的周边的上表面与上框架10之间; 塑料构件6的上表面被上框架10的内侧中间段限制; 并且上部框架10的下部和框架5用螺栓9紧固在一起。

公开(公告)号：US06528878B1

公开(公告)日：2003-03-04

申请号：US09631889

申请日：2000-08-04

申请人： Takahiro Daikoku ,  Kenichi Kasai ,  Toshitada Netsu ,  Koichi Koyano ,  Takayuki Uda

发明人： Takahiro Daikoku ,  Kenichi Kasai ,  Toshitada Netsu ,  Koichi Koyano ,  Takayuki Uda

IPC分类号： H01L2334

CPC分类号： H01L23/10 ,  H01L23/473 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/1626

摘要： According to the invention, a sealing top plate in a multi-chip module is formed from a ceramic with high thermal conductivity having a thermal expansion coefficient consistent with that of a multi-layer circuit substrate. A cooling flow path cover covering the entirety of cooling flow path grooves is formed as a separate metallic member. The back surface of the sealing top plate, on which are formed the cooling flow path grooves, is bonded directly to the back surface of a semiconductor device using solder. A thermal-conductive jacket with low thermal resistance is provided. A multi-chip module sealing frame is soldered to the edge of the sealing top plate. Furthermore, a sealing material such as an O-ring is simply interposed between the edge of the sealing top plate and the cooling water path cover, and tightening means is used to tighten the metallic cooling flow path cover and the multi-chip module sealing frame to each other.

摘要翻译： 根据本发明，多芯片模块中的密封顶板由具有与多层电路基板的热膨胀系数一致的高导热性的陶瓷形成。 覆盖整个冷却流路槽的冷却流路盖形成为单独的金属部件。 密封顶板的形成冷却流路槽的背面使用焊料直接接合在半导体装置的背面。 提供具有低热阻的导热护套。 多芯片模块密封框架焊接到密封顶板的边缘。 此外，诸如O形圈的密封材料简单地介于密封顶板的边缘和冷却水通道盖之间，并且紧固装置用于紧固金属冷却流路盖和多芯片模块密封框架 对彼此。

公开(公告)号：US06890799B2

公开(公告)日：2005-05-10

申请号：US10338485

申请日：2003-01-07

申请人： Takahiro Daikoku ,  Kenichi Kasai ,  Toshitada Netsu ,  Koichi Koyano ,  Takayuki Uda

发明人： Takahiro Daikoku ,  Kenichi Kasai ,  Toshitada Netsu ,  Koichi Koyano ,  Takayuki Uda

IPC分类号： H01L23/10 ,  H01L23/473 ,  H01L21/48 ,  H01L23/34 ,  H05K7/20

CPC分类号： H01L23/10 ,  H01L23/473 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/1626

摘要： According to the invention, a sealing top plate in a multi-chip module is formed from a ceramic with high thermal conductivity having a thermal expansion coefficient consistent with that of a multi-layer circuit substrate. A cooling flow path cover covering the entirety of cooling flow path grooves is formed as a separate metallic member. The back surface of the sealing top plate, on which are formed the cooling flow path grooves, is bonded directly to the back surface of a semiconductor device using solder. A thermal-conductive jacket with low thermal resistance is provided. A multi-chip module sealing frame is soldered to the edge of the sealing top plate. Furthermore, a sealing material such as an O-ring is simply interposed between the edge of the sealing top plate and the cooling water path cover, and tightening means is used to tighten the metallic cooling flow path cover and the multi-chip module sealing frame to each other.

摘要翻译： 根据本发明，多芯片模块中的密封顶板由具有与多层电路基板的热膨胀系数一致的高导热性的陶瓷形成。 覆盖整个冷却流路槽的冷却流路盖形成为单独的金属部件。 密封顶板的形成冷却流路槽的背面使用焊料直接接合在半导体装置的背面。 提供具有低热阻的导热护套。 多芯片模块密封框架焊接到密封顶板的边缘。 此外，诸如O形圈的密封材料简单地介于密封顶板的边缘和冷却水通道盖之间，并且紧固装置用于紧固金属冷却流路盖和多芯片模块密封框架 对彼此。

公开(公告)号：US06281575B1

公开(公告)日：2001-08-28

申请号：US09348260

申请日：1999-07-07

申请人： Toru Nishikawa ,  Masahide Harada ,  Kaoru Katayama ,  Takeshi Miitsu ,  Takayuki Uda ,  Takahiro Daikoku

发明人： Toru Nishikawa ,  Masahide Harada ,  Kaoru Katayama ,  Takeshi Miitsu ,  Takayuki Uda ,  Takahiro Daikoku

IPC分类号： H01L2310

CPC分类号： H01L23/433 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2224/0401

摘要： A multi-chip module is provided with a structure for disposing of a large amount of surplus solder at soldered portions. In this multi-chip module, a cooling member (structure) is soldered directly at the back side of heat generating member such as a semiconductor integrated circuit element. In order to dispose of the surplus solder, the present invention has a first metallized part formed at a cooling member which is larger than a second metallized part formed at the back side of semiconductor integrated circuit element which is solder with the first metallized part.

摘要翻译： 多芯片模块具有用于在焊接部分处设置大量剩余焊料的结构。 在该多芯片模块中，冷却构件（结构）直接焊接在诸如半导体集成电路元件的发热构件的背面。 为了配置剩余焊料，本发明具有形成在冷却部件处的第一金属化部分，其大于形成在与第一金属化部件焊接的半导体集成电路元件的背面的第二金属化部分。

公开(公告)号：US06355984B2

公开(公告)日：2002-03-12

申请号：US09828193

申请日：2001-04-09

申请人： Kazuhisa Miyamoto ,  Ryo Yamagata ,  Takayuki Uda

发明人： Kazuhisa Miyamoto ,  Ryo Yamagata ,  Takayuki Uda

IPC分类号： H01L2980

CPC分类号： H01L23/50 ,  H01L2224/16 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011

摘要： An input-output circuit cell includes an input-output circuit formed on a semiconductor chip and having a signal terminal and an electric source terminal and a plurality of input-output bumps connected to the signal and electric-source terminals of the input-output circuit through wirings respectively, the plurality of input-output bumps being made to correspond to the input-output circuit and arranged at a center in a plane of projection of the input-output circuit. Accordingly, the input-output circuit is disposed in an arbitrary position on the semiconductor chip.

摘要翻译： 输入输出电路单元包括形成在半导体芯片上并具有信号端子和电源端子的输入输出电路和连接到输入 - 输出电路的信号和电源端子的多个输入 - 输出凸块 通过布线分别使多个输入输出凸块对应于输入 - 输出电路并且布置在输入 - 输出电路的投影平面中的中心。 因此，输入输出电路配置在半导体芯片上的任意位置。

公开(公告)号：US5519658A

公开(公告)日：1996-05-21

申请号：US332078

申请日：1994-11-01

申请人： Takayuki Uda ,  Toshiro Hiramoto ,  Nobuo Tamba ,  Hisashi Ishida ,  Kazuhiro Akimoto ,  Masanori Odaka ,  Tasuku Tanaka ,  Jun Hirokawa ,  Masayuki Ohayashi

发明人： Takayuki Uda ,  Toshiro Hiramoto ,  Nobuo Tamba ,  Hisashi Ishida ,  Kazuhiro Akimoto ,  Masanori Odaka ,  Tasuku Tanaka ,  Jun Hirokawa ,  Masayuki Ohayashi

IPC分类号： H01L21/60 ,  H01L23/055 ,  H01L23/525 ,  H01L27/118 ,  G11C7/00

CPC分类号： H01L24/81 ,  H01L23/055 ,  H01L23/5256 ,  H01L24/11 ,  H01L27/118 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L23/3171 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/0107 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/3025

摘要： Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage. This allows a faulty circuit to be replaced with the corresponding redundancy circuit.

摘要翻译： 公开了半导体集成电路装置及其制造方法。 本发明的实施例是一种半导体芯片，其包括构成其中形成的冗余电路的一部分的保险丝，该保险丝由相同成分CCB凸块基底金属制成。 在CCB凸块基板金属的图案化期间，熔丝同时被图案化。 这涉及使用芯片中的电极导体图案的成分的至少一部分来形成保险丝。 保险丝的切割区域仅由构成基板的金属层中的一个构成。 半导体芯片的主平面具有至少形成在保险丝的切割区域上的保险丝保护膜，用于保护保险丝。 在操作中，使用冗余信号的开关控制下的开关MOSFET来选择两个传输路径中的一个，一个传送地址信号或解码信号，另一个传送参考电压。 这样可以将故障电路替换为相应的冗余电路。

公开(公告)号：US06222278B1

公开(公告)日：2001-04-24

申请号：US09648485

申请日：2000-08-28

申请人： Kazuhisa Miyamoto ,  Ryo Yamagata ,  Takayuki Uda

发明人： Kazuhisa Miyamoto ,  Ryo Yamagata ,  Takayuki Uda

IPC分类号： H01L2980

CPC分类号： H01L23/50 ,  H01L2224/16 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011

摘要： An input-output circuit cell includes an input-output circuit formed on a semiconductor chip and having a signal terminal and an electric source terminal and a plurality of input-output bumps connected to the signal and electric-source terminals of the input-output circuit through wirings respectively, the plurality of input-output bumps being made to correspond to the input-output circuit and arranged at a center in a plane of projection of the input-output circuit. Accordingly, the input-output circuit is disposed in an arbitrary position on the semiconductor chip.

公开(公告)号：US5049972A

公开(公告)日：1991-09-17

申请号：US544064

申请日：1990-06-26

申请人： Takayuki Uda ,  Tasuku Tanaka ,  Yoshiaki Emoto ,  Shigeo Kuroda

发明人： Takayuki Uda ,  Tasuku Tanaka ,  Yoshiaki Emoto ,  Shigeo Kuroda

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L25/16

CPC分类号： H01L25/165 ,  H01L23/3121 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041

摘要： A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the first opening and to remove the conductor film on the second resist film and the dummy conductor film on the first resist film.

摘要翻译： 一种制造半导体集成电路器件的方法，其中通过剥离技术在衬底的前表面上形成导体膜; 包括在其上未形成导体膜的基板表面的区域上形成第一抗蚀剂膜，在包括第一抗蚀剂膜和基板表面的导体膜形成区域的整个基板表面上形成第二抗蚀剂膜， 用于在第二抗蚀剂膜的导体膜形成区域中形成导体膜的第一开口，并且还在其中未形成导体膜的第二抗蚀剂膜的区域中提供用于形成虚设导体膜的第二开口， 在包括第一开口内的基板表面，第二开口内的第一抗蚀剂膜和第二抗蚀剂膜的整个基板表面上分别去除第二抗蚀剂膜和第一抗蚀剂膜，以便将导体膜留在内部 第一开口并且去除第二抗蚀剂膜上的导体膜和第一抗蚀剂膜上的虚设导体膜。

公开(公告)号：US07004760B2

公开(公告)日：2006-02-28

申请号：US10740545

申请日：2003-12-22

申请人： Katsuro Kawazoe ,  Takayuki Uda ,  Kouichi Yamamoto ,  Tsutomu Sakamoto ,  Maria Katsuki

发明人： Katsuro Kawazoe ,  Takayuki Uda ,  Kouichi Yamamoto ,  Tsutomu Sakamoto ,  Maria Katsuki

IPC分类号： H01R12/00

CPC分类号： H01R13/24 ,  H01R12/52

摘要： A connector is used for connecting a plurality of first terminals formed on a first electronic part to a plurality of respective second terminals formed on a second electronic part. The connector comprises an intermediate basis material having a spring characteristic, a plurality of first electrically conductive members provided on a first surface of the intermediate basis material, a plurality of second electrically conductive members provided on a second surface of the intermediate basis material, and wiring for connecting each of the first electrically conductive members to a corresponding one of the second electrically conductive members. Such electrically-conductive members may be columnar, tubular, spherical, and the like, and of appropriate width, thickness and material with regard to the characteristic requirements of the intermediate basis material.

摘要翻译： 连接器用于将形成在第一电子部件上的多个第一端子连接到形成在第二电子部件上的多个相应的第二端子。 连接器包括具有弹簧特性的中间基材料，设置在中间基材的第一表面上的多个第一导电构件，设置在中间基材的第二表面上的多个第二导电构件和布线 用于将每个第一导电构件连接到第二导电构件中的相应一个。 关于中间基材的特征要求，这种导电构件可以是柱状，管状，球形等，并且具有适当的宽度，厚度和材料。

公开(公告)号：US5360988A

公开(公告)日：1994-11-01

申请号：US903202

申请日：1992-06-23

申请人： Takayuki Uda ,  Toshiro Hiramoto ,  Nobuo Tamba ,  Hisashi Ishida ,  Kazuhiro Akimoto ,  Masanori Odaka ,  Tasuku Tanaka ,  Jun Hirokawa ,  Masayuki Ohayashi

发明人： Takayuki Uda ,  Toshiro Hiramoto ,  Nobuo Tamba ,  Hisashi Ishida ,  Kazuhiro Akimoto ,  Masanori Odaka ,  Tasuku Tanaka ,  Jun Hirokawa ,  Masayuki Ohayashi

IPC分类号： H01L21/60 ,  H01L23/055 ,  H01L23/525 ,  H01L27/118 ,  H01L23/48 ,  F42C19/12 ,  G06F15/60 ,  H01L21/285

CPC分类号： H01L24/81 ,  H01L23/055 ,  H01L23/5256 ,  H01L24/11 ,  H01L27/118 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L23/3171 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/0107 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/3025

摘要： Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients as those of a CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage. This allows a faulty circuit to be replaced with the corresponding redundancy circuit.

摘要翻译： 公开了半导体集成电路装置及其制造方法。 本发明的实施例是一种半导体芯片，其包括构成其中形成的冗余电路的一部分的熔丝，该熔丝由与CCB凸块基板金属相同的部件制成。 在CCB凸块基板金属的图案化期间，熔丝同时被图案化。 这涉及使用芯片中的电极导体图案的成分的至少一部分来形成保险丝。 保险丝的切割区域仅由构成基板的金属层中的一个构成。 半导体芯片的主平面具有至少形成在保险丝的切割区域上的保险丝保护膜，用于保护保险丝。 在操作中，使用冗余信号的开关控制下的开关MOSFET来选择两个传输路径中的一个，一个传送地址信号或解码信号，另一个传送参考电压。 这样可以将故障电路替换为相应的冗余电路。