公开(公告)号：US06274391B1

公开(公告)日：2001-08-14

申请号：US07966645

申请日：1992-10-26

申请人： Kurt P. Wachtler ,  David N. Walter ,  Larry J. Mowatt

发明人： Kurt P. Wachtler ,  David N. Walter ,  Larry J. Mowatt

IPC分类号： H01L2100

CPC分类号： H01L23/49816 ,  H01L23/055 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00012

摘要： A high density interconnect land grid array package device combines various electronic packaging techniques in a unique way to create a very thin, electrically and thermally high performance package for single or multiple semiconductor devices. A thin and mechanically stable substrate or packaging material (12) is selected that also has high thermal conductivity. Cavities (14) in the substrate or packaging material (12) accommodate one or more semiconductor devices that are attached directly to the substrate or packaging material. At least one of said semiconductor devices includes at least one optical receiver and/or transmitter. A thin film overlay (18) having multiple layers interconnects the one or more semiconductor devices to an array of pads (20) on a surface of the thin film overlay facing away from the substrate or packaging material. Solder balls (22), conductive adhesive or elastomeric connectors are attached to the pads to provide direct electrical and mechanical attachment means to other system hardware. In one embodiment of the invention, the optical receiver and/or transmitter receives and/or transmits light signals through the thin film overlay. In another embodiment of the invention, the optical receiver and/or transmitter receives and/or transmits light signals through holes (47) formed through the thin film overlay. The holes may be back filled with an optical quality material.

摘要翻译： 高密度互连焊盘阵列封装器件以独特的方式组合各种电子封装技术，以为单个或多个半导体器件创建非常薄的电气和热性能高的封装。 选择也具有高导热性的薄且机械稳定的基底或包装材料（12）。 衬底或包装材料（12）中的空腔（14）容纳一个或多个直接连接到衬底或包装材料的半导体器件。 所述半导体器件中的至少一个包括至少一个光接收器和/或发射器。 具有多个层的薄膜覆盖层（18）将一个或多个半导体器件与薄膜覆盖物表面上的衬垫阵列（20）相互互连，所述衬垫背面远离衬底或封装材料。 焊球（22），导电粘合剂或弹性连接器附接到焊盘，以向其他系统硬件提供直接的电和机械连接装置。 在本发明的一个实施例中，光接收器和/或发射器通过薄膜覆盖层接收和/或发射光信号。 在本发明的另一实施例中，光接收器和/或发射器通过穿过薄膜覆盖层形成的孔（47）接收和/或发射光信号。 孔可以用光学质量材料填充。

公开(公告)号：US06707124B2

公开(公告)日：2004-03-16

申请号：US09788075

申请日：2001-02-16

申请人： Kurt P. Wachtler ,  David N. Walter ,  Larry J. Mowatt

发明人： Kurt P. Wachtler ,  David N. Walter ,  Larry J. Mowatt

IPC分类号： H01L310203

CPC分类号： H01L23/49816 ,  H01L23/055 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00012

摘要： A high density interconnect device which creates a thin, electrically and thermally high performance package for semiconductor devices having a mechanically stable and high thermal conductivity substrate. Cavities in the substrate accommodate semiconductor devices attached directly to the substrate. The semiconductor devices include at least one optical receiver and/or transmitter. A thin film overlay having multiple layers interconnects the semiconductor devices to an array of pads on a surface of the thin film overlay facing away from the substrate. Connectors are attached to the pads to provide direct electrical and mechanical attachment to other system hardware. In one embodiment, the optical receiver and/or transmitter receives and/or transmits light signals through the thin film overlay. In another embodiment, the optical receiver and/or transmitter receives and/or transmits light signals through holes formed through the thin film overlay. The holes may be back filled with an optical quality material.

摘要翻译： 一种高密度互连器件，其为具有机械稳定且高导热性的衬底的半导体器件产生薄的，电性和热的高性能封装。 衬底中的腔容纳直接附着在衬底上的半导体器件。 半导体器件包括至少一个光接收器和/或发射器。 具有多个层的薄膜覆盖层将半导体器件与薄膜覆盖物的背离衬底的表面上的焊盘阵列互连。 连接器连接到焊盘，以提供与其他系统硬件的直接电气和机械连接。 在一个实施例中，光接收器和/或发射器通过薄膜覆盖层接收和/或发射光信号。 在另一实施例中，光接收器和/或发射器通过穿过薄膜覆盖层形成的孔接收和/或发射光信号。 孔可以用光学质量材料填充。

公开(公告)号：US06400573B1

公开(公告)日：2002-06-04

申请号：US08960994

申请日：1997-10-30

申请人： Larry J. Mowatt ,  David Walter

发明人： Larry J. Mowatt ,  David Walter

IPC分类号： H05K720

CPC分类号： H01L24/32 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/2402 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/3011 ,  H05K1/0203 ,  H05K1/117 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/066 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/09845 ,  H05K2201/10674 ,  H01L2924/00

摘要： A multi-chip integrated circuit module includes a supporting layer of laminate material over which a high-density interconnect structure is formed. The laminate layer includes a first upper laminate layer (10) having a hole (14) disposed therein for receiving an integrated circuit chip die (56). A lower core laminate layer (16) having a conductive layer (18) and conductive layer (20) disposed on opposite sides thereof is laminated to the lower surface of the layer (10). Plated-through holes (36), (38) and (40) are formed through the two layers (10) and (16) to connect the conductive layer (20) with a conductive layer (12) on the upper surface of the layer (10). A high-density interconnect layer includes two laminate layers (126) and (138), each having vias formed therethrough and via interconnect structures disposed on the surfaces thereof. The via interconnect structures in the layer (126) allow for connections from the die (56) to the conductive layer (12). The via interconnect structures formed in the layer (138) allow interconnection from the upper surface of layer (138) to via interconnects formed in the layer (126). An I/O connector is interfaced with select ones of the plated-through holes with pins (162) and (164). This allows an interface from the module to an operating system through pins (166).

摘要翻译： 多芯片集成电路模块包括层叠材料的支撑层，在其上形成高密度互连结构。 层压层包括第一上层叠层（10），其具有设置在其中的用于接收集成电路芯片模具（56）的孔（14）。 具有导电层（18）和设置在其相对侧上的导电层（20）的下芯层压层（16）被层压到层（10）的下表面。 通过两层（10）和（16）形成电镀通孔（36），（38）和（40），以将导电层（20）与层的上表面上的导电层（12）连接 （10）。 高密度互连层包括两个层压层（126）和（138），每个层叠层（126）和（138）各自具有穿过其中形成的通孔，并且经由布置在其表面上的互连结构。 层（126）中的通孔互连结构允许从管芯（56）到导电层（12）的连接。 形成在层（138）中的通孔互连结构允许从层（138）的上表面到在层（126）中形成的通孔互连的互连。 I / O连接器与选择的具有引脚（162）和（164）的电镀通孔相连接。 这允许通过引脚（166）从模块到操作系统的接口。

公开(公告)号：US4776804A

公开(公告)日：1988-10-11

申请号：US12703

申请日：1987-02-05

申请人： Larry K. Johnson ,  Austin S. O'Malley ,  Robert M. Fife ,  Walter L. Walas ,  Robert K. Peterson ,  Larry J. Mowatt ,  Maurice M. Guy

发明人： Larry K. Johnson ,  Austin S. O'Malley ,  Robert M. Fife ,  Walter L. Walas ,  Robert K. Peterson ,  Larry J. Mowatt ,  Maurice M. Guy

IPC分类号： H01R12/50 ,  H01R12/52 ,  H05K1/14 ,  H01R9/09

CPC分类号： H01R23/70 ,  H01R12/722 ,  H05K1/14 ,  H01R12/52 ,  H05K2201/044 ,  Y10T29/49144

摘要： A circuit board system resiliently mounts a plurality of daughter boards with high circuit interconnection density on a mother board using pairs of mating connectors having welded contact members accommodated in novel arrangements in the respective connectors to permit high density of electrical interconnection with convenience and reliability. Contact parts of substantial size are welded into contacts in one connector to detachably interconnect with contact parts of similar size in mating connector to improve interconnection releability. Novel contact arrangements permit accommodation of those parts of substantial size in the mating connectors. Sheet metal spring or post parts welded into the contacts in both connectors permit the contacts to be conveniently loaded into connector bodies and permit large numbers of contact springs or posts to be soldered to terminal pads or circuit paths on mother or daughter boards with high density. Temporary fixtures mount on connectors to facilitate precise soldering of leaf springs to very closely spaced terminal pads on daughter boards; resilient mounting of the mother board facilitate daughter board engagement with heat sinks; and organizer plates fit on extending ends of connector contact posts to facilitate their insertion into mother board mounting holes with high interconnection density.

公开(公告)号：US4882454A

公开(公告)日：1989-11-21

申请号：US155462

申请日：1988-02-12

申请人： Robert K. Peterson ,  Larry J. Mowatt ,  Aaron D. Poteet

发明人： Robert K. Peterson ,  Larry J. Mowatt ,  Aaron D. Poteet

IPC分类号： H05K1/02 ,  H05K1/05 ,  H05K3/40 ,  H05K3/44 ,  H05K3/46

CPC分类号： H05K1/0206 ,  H05K3/403 ,  H05K1/056 ,  H05K2201/0919 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09709 ,  H05K2201/09781 ,  H05K3/445 ,  H05K3/4608 ,  Y10T29/49149 ,  Y10T29/49155

摘要： A printed wiring board is comprised of a combination of layers providing a good thermal match with surface mount components. The board consists of a core surrounded by multiple layers of dielectric and conductive materials optimized for their thermal expansion qualities. The core is also used as a heat sink for drawing excess heat from the components. An integral thermal interface region is used to dissipate the heat from the core.

摘要翻译： 印刷线路板由提供与表面安装部件良好热匹配的层的组合构成。 该电路板包含一个被多层电介质和导电材料包围的核心，它们的热膨胀性质优化。 核心也用作从组件中抽出多余热量的散热器。 使用整体热界面区域来散发来自芯体的热量。

公开(公告)号：US5432677A

公开(公告)日：1995-07-11

申请号：US180092

申请日：1994-01-11

申请人： Larry J. Mowatt ,  David Walter

发明人： Larry J. Mowatt ,  David Walter

IPC分类号： H01L23/538 ,  H01L25/065 ,  H05K1/18 ,  H05K7/20

CPC分类号： H01L24/32 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H05K1/117 ,  H05K1/185 ,  H01L2224/2402 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0203 ,  H05K2201/066 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/09845 ,  H05K3/4602 ,  Y10T29/4913

摘要： A multi-chip integrated circuit module includes a supporting layer of laminate material over which a high-density interconnect structure is formed. The laminate layer includes a first upper laminate layer (10) having a hole (14) disposed therein for receiving an integrated circuit chip die (56). A lower core laminate layer (16) having a conductive layer (18) and conductive layer (20) disposed on opposite sides thereof is laminated to the lower surface of the layer (10). Plated-through holes (36), (38) and (40) are formed through the two layers (10) and (16) to connect the conductive layer (20) with a conductive layer (12) on the upper surface of the layer (10). A high-density interconnect layer includes two laminate layers (126) and (138), each having vias formed therethrough and via interconnect structures disposed on the surfaces thereof. The via interconnect structures in the layer (126) allow for connections from the die (56) to the conductive layer (12). The via interconnect structures formed in the layer (138) allow interconnection from the upper surface of layer (138) to via interconnects formed in the layer (126). An I/O connector is interfaced with select ones of the plated-through holes with pins (162) and (164). This allows an interface from the module to an operating system through pins (166).

公开(公告)号：US5306670A

公开(公告)日：1994-04-26

申请号：US15510

申请日：1993-02-09

申请人： Larry J. Mowatt ,  David Walter

发明人： Larry J. Mowatt ,  David Walter

IPC分类号： H01L23/538 ,  H01L25/065 ,  H05K1/18 ,  H01L21/60

CPC分类号： H01L24/32 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H05K1/117 ,  H05K1/185 ,  H01L2224/2402 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0203 ,  H05K2201/066 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/09845 ,  H05K3/4602 ,  Y10T29/4913

摘要： A multi-chip integrated circuit module includes a supporting layer of laminate material over which a high-density interconnect structure is formed. The laminate layer includes a first upper laminate layer (10) having a hole (14) disposed therein for receiving an integrated circuit chip die (56). A lower core laminate layer (16) having a conductive layer (18) and conductive layer (20) disposed on opposite sides thereof is laminated to the lower surface of the layer (10). Plated-through holes (36), (38) and (40) are formed through the two layers (10) and (16) to connect the conductive layer (20) with a conductive layer (12) on the upper surface of the layer (10). A high-density interconnect layer includes two laminate layers (126) and (138), each having vias formed therethrough and via interconnect structures disposed on the surfaces thereof. The via interconnect structures in the layer (126) allow for connections from the die (56) to the conductive layer (12). The via interconnect structures formed in the layer (138) allow interconnection from the upper surface of layer (138) to via interconnects formed in the layer (126). An I/O connector is interfaced with select ones of the plated-through holes with pins (162) and (164). This allows an interface from the module to an operating system through pins (166).

摘要翻译： 多芯片集成电路模块包括层叠材料的支撑层，在其上形成高密度互连结构。 层压层包括第一上层叠层（10），其具有设置在其中的用于接收集成电路芯片模具（56）的孔（14）。 具有导电层（18）和设置在其相对侧上的导电层（20）的下芯层压层（16）被层压到层（10）的下表面。 通过两层（10）和（16）形成电镀通孔（36），（38）和（40），以将导电层（20）与层的上表面上的导电层（12）连接 （10）。 高密度互连层包括两个层压层（126）和（138），每个层叠层（126）和（138）各自具有穿过其中形成的通孔，并且经由布置在其表面上的互连结构。 层（126）中的通孔互连结构允许从管芯（56）到导电层（12）的连接。 形成在层（138）中的通孔互连结构允许从层（138）的上表面到在层（126）中形成的通孔互连的互连。 I / O连接器与选择的具有引脚（162）和（164）的电镀通孔相连接。 这允许通过引脚（166）从模块到操作系统的接口。

公开(公告)号：US4963697A

公开(公告)日：1990-10-16

申请号：US155461

申请日：1988-02-12

申请人： Robert K. Peterson ,  Larry J. Mowatt ,  Aaron D. Poteet

发明人： Robert K. Peterson ,  Larry J. Mowatt ,  Aaron D. Poteet

IPC分类号： H05K1/02 ,  H05K1/05 ,  H05K3/40 ,  H05K3/44 ,  H05K3/46

CPC分类号： H05K1/0209 ,  H05K1/0207 ,  H05K3/445 ,  H05K1/0206 ,  H05K1/056 ,  H05K2201/068 ,  H05K2201/0919 ,  H05K2201/09509 ,  H05K2201/09781 ,  H05K2203/143 ,  H05K3/403 ,  H05K3/4608 ,  Y10T29/49128 ,  Y10T29/49155

摘要： A printed wiring board is comprised of a combination of layers providing a good thermal match with surface mount components. The board consists of a core surrounded by multiple layers of dielectric and conductive materials optimized for their thermal expansion qualities. The core is also used as the tooling plate during manufacture. Side-to-side interconnects are made by blind-plated vias and through-holes in the core.

摘要翻译： 印刷线路板由提供与表面安装部件良好热匹配的层的组合构成。 该电路板包含一个被多层电介质和导电材料包围的核心，它们的热膨胀性质优化。 在制造过程中，芯也用作工具板。 侧面到侧面的互连通过盲孔通孔和芯中的通孔制成。