公开(公告)号：US08753981B2

公开(公告)日：2014-06-17

申请号：US13092434

申请日：2011-04-22

申请人： Kyle K. Kirby ,  Kunal R. Parekh ,  Philip J. Ireland ,  Sarah A. Niroumand

发明人： Kyle K. Kirby ,  Kunal R. Parekh ,  Philip J. Ireland ,  Sarah A. Niroumand

IPC分类号： H01L21/44 ,  H01L21/311

CPC分类号： H01L23/5226 ,  H01L21/02063 ,  H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L2224/13025 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.

摘要翻译： 具有通硅通孔的微电子器件及其相关制造方法。 一种用于形成钨硅通孔的方法的一个实施例，包括形成具有侧壁的开口，使得所述开口延伸穿过已经形成有微电子结构的衬底的至少一部分。 该方法可以进一步包括用介电材料衬里侧壁，在介电材料上沉积钨，使得空腔延伸穿过钨的至少一部分，并用多晶硅材料填充空腔。

公开(公告)号：US20120267786A1

公开(公告)日：2012-10-25

申请号：US13092434

申请日：2011-04-22

申请人： Kyle K. Kirby ,  Kunal R. Parekh ,  Philip J. Ireland ,  Sarah A. Niroumand

发明人： Kyle K. Kirby ,  Kunal R. Parekh ,  Philip J. Ireland ,  Sarah A. Niroumand

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L23/5226 ,  H01L21/02063 ,  H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L2224/13025 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.

摘要翻译： 具有通硅通孔的微电子器件及其相关制造方法。 一种用于形成钨硅通孔的方法的一个实施例，包括形成具有侧壁的开口，使得所述开口延伸穿过已经形成有微电子结构的衬底的至少一部分。 该方法可以进一步包括用介电材料衬里侧壁，在介电材料上沉积钨，使得空腔延伸穿过钨的至少一部分，并用多晶硅材料填充空腔。

公开(公告)号：US20110193226A1

公开(公告)日：2011-08-11

申请号：US12701800

申请日：2010-02-08

申请人： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

发明人： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/488

CPC分类号： H01L21/76877 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/76805 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05552

摘要： Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

摘要翻译： 本文公开了具有贯穿衬底互连和相关制造方法的微电子器件。 在一个实施例中，半导体器件包括承载第一和第二金属化层的半导体衬底。 第二金属化层与半导体衬底间隔开，其间具有第一金属化层。 半导体器件还包括至少部分延伸穿过半导体衬底的导电互连。 第一金属化层经由第二金属化层与导电互连电接触。

公开(公告)号：US08907457B2

公开(公告)日：2014-12-09

申请号：US12701800

申请日：2010-02-08

申请人： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

发明人： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

IPC分类号： H01L29/40 ,  H01L25/00 ,  H01L21/768 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L21/76877 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/76805 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05552

摘要： Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

摘要翻译： 本文公开了具有贯穿衬底互连和相关制造方法的微电子器件。 在一个实施例中，半导体器件包括承载第一和第二金属化层的半导体衬底。 第二金属化层与半导体衬底间隔开，其间具有第一金属化层。 半导体器件还包括至少部分延伸穿过半导体衬底的导电互连。 第一金属化层经由第二金属化层与导电互连电接触。

公开(公告)号：US08404587B2

公开(公告)日：2013-03-26

申请号：US13160363

申请日：2011-06-14

申请人： Kyle K. Kirby ,  Kunal R. Parekh

发明人： Kyle K. Kirby ,  Kunal R. Parekh

IPC分类号： H01L21/44

CPC分类号： H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L27/0694 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66568 ,  H01L29/78 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548

摘要： Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US08629057B2

公开(公告)日：2014-01-14

申请号：US13241059

申请日：2011-09-22

申请人： Kyle K. Kirby ,  Kunal R. Parekh

发明人： Kyle K. Kirby ,  Kunal R. Parekh

IPC分类号： H01L21/4763

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.

摘要翻译： 公开了具有单一通孔和通孔端子的半导体衬底以及相关联的系统和方法。 根据特定实施例的代表性方法包括在半导体衬底中形成盲通孔，将保护层施加到通孔的侧壁表面，以及通过从通孔的端面选择性地去除衬底材料形成端子开口，同时 防止施加保护涂层的去除衬底材料。 该方法还可以包括在导通孔和端子开口中设置导电材料，以形成与通路中的导电材料整体的导电端子。 然后可以除去与端子相邻的衬底材料以露出端子，然后该端子可以连接到衬底外部的导电结构。

公开(公告)号：US08030780B2

公开(公告)日：2011-10-04

申请号：US12253121

申请日：2008-10-16

申请人： Kyle K. Kirby ,  Kunal R. Parekh

发明人： Kyle K. Kirby ,  Kunal R. Parekh

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.

摘要翻译： 公开了具有单一通孔和通孔端子的半导体衬底以及相关联的系统和方法。 根据特定实施例的代表性方法包括在半导体衬底中形成盲通孔，将保护层施加到通孔的侧壁表面，以及通过从通孔的端面选择性地去除衬底材料形成端子开口，同时 防止施加保护涂层的去除衬底材料。 该方法还可以包括在导通孔和端子开口中设置导电材料，以形成与通路中的导电材料整体的导电端子。 然后可以除去与端子相邻的衬底材料以露出端子，然后该端子可以连接到衬底外部的导电结构。

公开(公告)号：US20100096759A1

公开(公告)日：2010-04-22

申请号：US12253121

申请日：2008-10-16

申请人： Kyle K. Kirby ,  Kunal R. Parekh

发明人： Kyle K. Kirby ,  Kunal R. Parekh

IPC分类号： H01L21/768 ,  H01L21/50 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.

摘要翻译： 公开了具有单一通孔和通孔端子的半导体衬底以及相关联的系统和方法。 根据特定实施例的代表性方法包括在半导体衬底中形成盲通孔，将保护层施加到通孔的侧壁表面，以及通过从通孔的端面选择性地去除衬底材料形成端子开口，同时 防止施加保护涂层的去除衬底材料。 该方法还可以包括在导通孔和端子开口中设置导电材料，以形成与通路中的导电材料整体的导电端子。 然后可以除去与端子相邻的衬底材料以露出端子，然后该端子可以连接到衬底外部的导电结构。

公开(公告)号：US20120009776A1

公开(公告)日：2012-01-12

申请号：US13241059

申请日：2011-09-22

申请人： Kyle K. Kirby ,  Kunal R. Parekh

发明人： Kyle K. Kirby ,  Kunal R. Parekh

IPC分类号： H01L21/768 ,  H01L21/283

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.

摘要翻译： 公开了具有单一通孔和通孔端子的半导体衬底以及相关联的系统和方法。 根据特定实施例的代表性方法包括在半导体衬底中形成盲通孔，将保护层施加到通孔的侧壁表面，以及通过从通孔的端面选择性地去除衬底材料形成端子开口，同时 防止施加保护涂层的去除衬底材料。 该方法还可以包括在导通孔和端子开口中设置导电材料，以形成与通路中的导电材料整体的导电端子。 然后可以除去与端子相邻的衬底材料以露出端子，然后该端子可以连接到衬底外部的导电结构。

公开(公告)号：US09343665B2

公开(公告)日：2016-05-17

申请号：US12166604

申请日：2008-07-02

申请人： Nishant Sinha ,  John Smythe ,  Bhaskar Srinivasan ,  Gurtej S. Sandhu ,  Joseph Neil Greeley ,  Kunal R. Parekh

发明人： Nishant Sinha ,  John Smythe ,  Bhaskar Srinivasan ,  Gurtej S. Sandhu ,  Joseph Neil Greeley ,  Kunal R. Parekh

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1683 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.

摘要翻译： 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 含金属氧化物的材料形成在第一导电电极上。 蚀刻停止材料沉积在包含金属氧化物的材料上。 导电材料沉积在蚀刻停止材料上。 包含所接收的导电材料的存储单元的第二导电电极形成在蚀刻停止材料上。 这样包括通过导电材料蚀刻以相对于蚀刻停止材料停止并且形成非易失性电阻氧化物存储单元，以包括具有包含金属氧化物的材料和其间的蚀刻停止材料的第一和第二导电电极。 考虑其他实现。