摘要:
A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.
摘要:
A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.
摘要:
The present invention provides for a heterogeneous low k dielectric comprising a main layer and a sub-layer. The main layer comprises a first low k dielectric material with a first low k dielectric constant and the sub-layer comprises a second low k dielectric material with a second low k dielectric constant. The sub-layer directly adjoins the main layer, and the second low k dielectric constant is greater than the first low k dielectric constant by more than 0.1.
摘要:
A method for manufacturing an integrated circuit is provided. In one example, the method includes forming a substantially nitrogen-free silicon carbide layer over a substrate using a methyl silicate gas.
摘要:
A semiconductor device and method for forming the device wherein the device includes a substrate; a dielectric insulating layer formed overlying the substrate; a metal filled dual damascene structure formed in the dielectric insulating layer, wherein the metal filled dual damascene structure includes a via portion and a trench portion; and at least one intervening dielectric layer in compressive stress formed in the dielectric insulating layer and disposed at a level adjacent to at least one of the via portion and the trench portion of the metal filled dual damascene structure.
摘要:
A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.
摘要:
An interconnect structure with improved reliability is provided. The interconnect structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metallic wiring in the dielectric layer; a pre-layer over the metallic wiring, wherein the pre-layer contains boron; and a metal cap over the pre-layer, wherein the metal cap contains tungsten, and wherein the pre-layer and the metal cap are formed of different materials.
摘要:
Semiconductor devices with composite etch stop layers and methods of fabrication thereof. An semiconductor device with a composite etch stop layer includes a substrate having a conductive member, a first etch stop layer on the substrate and the conductive member, a second etch stop layer and a dielectric layer sequentially over the second etch stop layer, having a conductive layer therein down through the dielectric layer, the second etch stop layer and the first etch stop layer to the conductive member.
摘要:
Semiconductor devices with composite etch stop layers and methods of fabrication thereof. An semiconductor device with a composite etch stop layer includes a substrate having a conductive member, a first etch stop layer on the substrate and the conductive member, a second etch stop layer and a dielectric layer sequentially over the second etch stop layer, having a conductive layer therein down through the dielectric layer, the second etch stop layer and the first etch stop layer to the conductive member.
摘要:
The present invention relates to an improved integrated circuit structure including adjacent conductive and dielectric layers having a continuous, planar top surface, produced by a process which includes treating the surface with a silane compound, followed by depositing an etch stop layer over the surface, wherein a glue layer is not applied to the surface.