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    Graphics Processing Unit and High Bandwidth Memory Integration Using Integrated Interface and Silicon Interposer
    1.
    发明申请
    Graphics Processing Unit and High Bandwidth Memory Integration Using Integrated Interface and Silicon Interposer 有权

    公开(公告)号：US20250118722A1

    公开(公告)日：2025-04-10

    申请号：US18982102

    申请日：2024-12-16

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Owen R. Fay

    IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/00

    Abstract: A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.

    Stacked interposer structures
    2.
    发明授权
    Stacked interposer structures 有权

    公开(公告)号：US12218119B2

    公开(公告)日：2025-02-04

    申请号：US17931284

    申请日：2022-09-12

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Chan H. Yoo

    IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/16

    Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.

    SEMICONDUCTOR ASSEMBLIES WITH SYSTEM AND METHOD FOR SMOOTHING SURFACES OF 3D STRUCTURES
    6.
    发明公开
    SEMICONDUCTOR ASSEMBLIES WITH SYSTEM AND METHOD FOR SMOOTHING SURFACES OF 3D STRUCTURES 审中-公开

    公开(公告)号：US20230317511A1

    公开(公告)日：2023-10-05

    申请号：US18111496

    申请日：2023-02-17

    Applicant: Micron Technology, Inc.

    Inventor： Andrew M. Bayless ,  Brandon P. Wirz ,  Owen R. Fay

    IPC: H01L21/768 ,  H01L21/02 ,  G03F7/004 ,  G03F7/20

    CPC classification number: H01L21/76801 ,  G03F7/004 ,  G03F7/20 ,  H01L21/02348

    Abstract: A method for smoothing structures formed of curable materials on a semiconductor device includes applying a layer of photo-responsive material on a substrate. The photo-responsive material is exposed to ultraviolet light through a grayscale gradient mask. Subsequent to removing unwanted portions of the photo-responsive material, the photo-responsive material that remains on the substrate is cured. During the curing process, the temperature is increased from a starting temperature to a final cure temperature over a first time period that allows the photo-responsive material to cross-flow. The temperature of the photo-responsive material is maintained at approximately the final cure temperature for a second time period, and then the temperature of the photo-responsive material is decreased to a predetermined finish temperature over a third time period.

    High density pillar interconnect conversion with stack to substrate connection
    7.
    发明授权
    High density pillar interconnect conversion with stack to substrate connection 有权

    公开(公告)号：US11631644B2

    公开(公告)日：2023-04-18

    申请号：US17221537

    申请日：2021-04-02

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

    IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

    Abstract: A semiconductor device assembly can include a semiconductor device having a substrate and vias electrically connected to circuitry of the semiconductor device. Individual vias can have an embedded portion extending from the first side to the second side of the substrate and an exposed portion projecting from the second side of the substrate. The assembly can include a density-conversion connector comprising a connector substrate and a first array of contacts formed at the first side thereof, the first array of contacts occupying a first footprint area on the first side thereof, and wherein individual contacts of the first array are electrically connected to the exposed portion of a corresponding via of the semiconductor device. The assembly can include a second array of contacts electrically connected to the first array, formed at the second side of the connector substrate, and occupying a second footprint area larger than the first footprint area.

    High density pillar interconnect conversion with stack to substrate connection
    9.
    发明授权
    High density pillar interconnect conversion with stack to substrate connection 有权

    公开(公告)号：US11587912B2

    公开(公告)日：2023-02-21

    申请号：US17383304

    申请日：2021-07-22

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

    IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L21/60

    Abstract: A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.

    Semiconductor assemblies with redistribution structures for die stack signal routing
    10.
    发明授权
    Semiconductor assemblies with redistribution structures for die stack signal routing 有权

    公开(公告)号：US11552045B2

    公开(公告)日：2023-01-10

    申请号：US17100610

    申请日：2020-11-20

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Madison E. Wale ,  James L. Voelz ,  Dylan W. Southern ,  Dustin L. Holloway

    IPC: H01L23/00

    Abstract: Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly comprises a die stack including a plurality of semiconductor dies, and a routing substrate mounted on the die stack. The routing substrate includes an upper surface having a redistribution structure. The semiconductor assembly also includes a plurality of electrical connectors coupling the redistribution structure to at least some of the semiconductor dies. The semiconductor assembly further includes a controller die mounted on the routing substrate. The controller die includes an active surface that faces the upper surface of the routing substrate and is electrically coupled to the redistribution structure, such that the routing substrate and the semiconductor dies are electrically coupled to the controller die via the redistribution structure.

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