公开(公告)号：US20030017626A1

公开(公告)日：2003-01-23

申请号：US09909941

申请日：2001-07-23

申请人： MOTOROLA INC.

发明人： Lyndee L. Hilt ,  Jay A. Curless ,  Paige M. Holm

IPC分类号： H01L021/00 ,  H01L021/336

CPC分类号： C30B25/18 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/02658

摘要： High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. The strain relief provided by the amorphous interface layer reduces the amount of defects, such as dislocations, occurring in the semiconductor structure and allows a higher crystalline quality to be obtained. The propagation of dislocations can further be controlled by applying a strain controlling element to the semiconductor structure. The strain controlling element may include a distorting material applied to the substrate and having a different thermal property than the substrate so that the distorting material can induce a strain in the semiconductor structure to compensate for strain induced in the semiconductor structure during its manufacture. The strain controlling element may also include a pattern growth for controlling the location of dislocations in the semiconductor structure.

摘要翻译： 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 由非晶界面层提供的应变消除减少在半导体结构中发生的诸如位错的缺陷的量，并且允许获得更高的结晶质量。 通过向半导体结构施加应变控制元件可以进一步控制位错的传播。 应变控制元件可以包括施加到衬底上并且具有与衬底不同的热性能的变形材料，使得变形材料可以在半导体结构中引起应变以补偿在其制造期间在半导体结构中诱发的应变。 应变控制元件还可以包括用于控制半导体结构中位错位置的图案生长。

公开(公告)号：US20030027408A1

公开(公告)日：2003-02-06

申请号：US09921905

申请日：2001-08-06

申请人： MOTOROLA, INC.

发明人： Jay A. Curless

IPC分类号： H01L021/20

CPC分类号： C30B25/18 ,  C30B25/02 ,  C30B29/22 ,  H01L21/02197 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/31691

摘要： High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer has a lattice registry to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. The layers of the semiconductor structure may be manufactured in such a way as to control the formation of anti-phase domains so that the structure may operate without the deleterious effects associated with such defects. Such manufacture may include heat treating the substrate to essentially or completely eliminate single steps (anti-phase domains) by forming double steps that can transfer to the oxide interface layer and suppress the formation of anti-phase domains by forming double step therein, in preference to single steps.

摘要翻译： 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层具有与下面的硅晶片和上覆的单晶材料层两者的晶格对准。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 半导体结构的层可以以控制反相畴的形成的方式制造，使得结构可以在没有与这种缺陷相关联的有害影响的情况下运行。 这样的制造可以包括通过形成可以转移到氧化物界面层并且通过在其中形成双重步骤来抑制反相结构域的形成的双重步骤来热处理基材以基本上或完全消除单个步骤（反相畴） 单步。

公开(公告)号：US20030024471A1

公开(公告)日：2003-02-06

申请号：US09921910

申请日：2001-08-06

申请人： MOTOROLA, INC.

发明人： Albert Alec Talin ,  Jay A. Curless ,  Ravindranath Droopad ,  Joyce Yamamoto

IPC分类号： H01L021/00

CPC分类号： C30B25/18 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/268

摘要： Semiconductor structures are provided with high quality epitaxial layers of monocrystalline materials grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and an overlying monocrystalline material layer. With laser assisted fabrication, a laser energy source is used to preclean the accommodating buffer layer, to excite the accommodating buffer layer to higher energy to promote two-dimensional growth, and to amorphize the accommodating buffer layer, without requiring transport of the semiconductor structure from one environment to another. When chemical vapor deposition is utilized, the laser radiation source can be employed to crack volatile chemical precursors while selectively heating the growth substrate to enable selective deposition.

摘要翻译： 半导体结构设置有通过形成用于生长单晶层的柔性衬底生长在诸如大硅晶片的单晶衬底上生长的单晶材料的高质量外延层。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 容纳缓冲层与下面的硅晶片和上覆单晶材料层晶格匹配。 通过激光辅助制造，使用激光能量源来清除容纳缓冲层，将容纳缓冲层激发到更高的能量以促进二维生长，并使收容缓冲层非晶化，而不需要将半导体结构从 一个环境到另一个环境。 当使用化学气相沉积时，可以使用激光辐射源来裂化挥发性化学前体，同时选择性地加热生长衬底以实现选择性沉积。

公开(公告)号：US20030015704A1

公开(公告)日：2003-01-23

申请号：US09910023

申请日：2001-07-23

申请人： MOTOROLA, INC.

发明人： Jay A. Curless

IPC分类号： H01L027/108 ,  H01L029/04 ,  H01L029/76 ,  H01L031/036 ,  H01L021/00 ,  H01L021/469 ,  H01L021/31

CPC分类号： H01L21/02658 ,  C30B25/18 ,  H01L21/02043 ,  H01L21/02046 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/2205 ,  H01L21/31691

摘要： Process for fabrication of semiconductor structures and devices (267, 270) including an intermediate surface cleaning procedure performed to remove metal contaminants in the surface region (262) of a seed film (261) of a monocrystalline compound semiconductor material that is formed overlying a perovskite oxide film (24), which is the source of the contaminants. After removal of the contaminated surface region (262), monocrystalline compound semiconductor material is regrown on the remaining seed film (264) to form a layer (266) having a thickness suitable for forming devices therein.

摘要翻译： 包括中间表面清洁程序的半导体结构和器件（267,270）的制造方法，该中间表面清洁程序用于去除覆盖钙钛矿的单晶化合物半导体材料的种子膜（261）的表面区域（262）中的金属污染物 氧化膜（24），这是污染物的来源。 在去除被污染的表面区域（262）之后，单晶化合物半导体材料在剩余的种子膜（264）上重新生长，以形成具有适于在其中形成器件的厚度的层（266）。

公开(公告)号：US20010023660A1

公开(公告)日：2001-09-27

申请号：US09871958

申请日：2001-06-04

申请人： MOTOROLA, INC.

发明人： Zhiyi Yu ,  Ravindranath Droopad ,  Corey Daniel Overgaard ,  Jamal Ramdani ,  Jay A. Curless ,  Jerald A. Hallmark ,  William J. Ooms ,  Jun Wang

IPC分类号： C30B025/00 ,  C30B023/00 ,  C30B028/12 ,  C30B028/14

CPC分类号： C30B23/02 ,  C30B25/02 ,  C30B29/16 ,  C30B29/30

摘要： A method for fabricating a semiconductor structure comprises the steps of providing a silicon substrate (10) having a surface (12); forming on the surface of the silicon substrate an interface (14) comprising a single atomic layer of silicon, oxygen, and a metal; and forming one or more layers of a single crystal oxide (26) on the interface. The interface comprises an atomic layer of silicon, oxygen, and a metal in the form XSiO2, where X is a metal.

公开(公告)号：US20030017720A1

公开(公告)日：2003-01-23

申请号：US09908891

申请日：2001-07-20

申请人： MOTOROLA, INC.

发明人： Jay A. Curless ,  Lyndee L. Hilt

IPC分类号： H01L021/31 ,  H01L021/469

CPC分类号： C30B25/02 ,  C30B25/18 ,  C30B29/40 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02197 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/31691

摘要： High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer has lattice registry to both the underlying silicon wafer and the overlying monocrystalline material layer. Formation of a compliant substrate preferably includes utilizing enhanced epitaxy of a surfactant template layer. The surfactant template layer may be formed by depositing an organometallic compound on the accommodating buffer layer using atomic layer epitaxy. In certain preferred embodiments, the organometallic compound is an aluminum-containing compound.

摘要翻译： 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层具有与底层硅晶片和上覆单晶材料层两者的晶格注册。 顺应性底物的形成优选包括利用表面活性剂模板层的增强的外延。 可以通过使用原子层外延在容纳缓冲层上沉积有机金属化合物来形成表面活性剂模板层。 在某些优选实施方案中，有机金属化合物是含铝化合物。

公开(公告)号：US20030015760A1

公开(公告)日：2003-01-23

申请号：US09908695

申请日：2001-07-20

申请人： Motorola, Inc.

发明人： Jay A. Curless ,  Albert A. Talin

IPC分类号： H01L021/8238 ,  H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119

CPC分类号： H01L21/8258 ,  H01L21/02197 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/31691 ,  H01L21/324

摘要： Process for fabricating a semiconductor structure (500) comprising depositing a capping layer (67) on a portion (54) of a monocrystalline compound semiconductor layer (66) overlying a template film (64), a monocrystalline perovskite oxide material (60), an amorphous oxide layer (62) and a monocrystalline silicon substrate (52), and then exposing at least one surface region (531) of the single crystal silicon substrate (52) into which a CMOS circuit (56) is formed in a CMOS region (53), followed by heating the CMOS circuit (56) to anneal the CMOS region (53) and, optionally, concurrently transform the monocrystalline perovskite oxide film (60) into an amorphous perovskite oxide film (136). The resulting composite semiconductor structure (500) is also encompassed.

摘要翻译： 一种用于制造半导体结构（500）的方法，包括在覆盖在模板膜（64）上的单晶化合物半导体层（66）的一部分（54）上沉积覆盖层（67），单晶钙钛矿氧化物材料（60）， 非晶氧化物层（62）和单晶硅衬底（52），然后暴露在CMOS区域中形成有CMOS电路（56）的单晶硅衬底（52）的至少一个表面区域（531） 53），然后加热CMOS电路（56）以退火CMOS区域（53），并且任选地同时将单晶钙钛矿氧化物膜（60）转变成无定形钙钛矿氧化物膜（136）。 所得的复合半导体结构（500）也包括在内。

公开(公告)号：US20030015731A1

公开(公告)日：2003-01-23

申请号：US09910020

申请日：2001-07-23

申请人： Motorola, Inc.

发明人： Jay A. Curless ,  Lyndee L. Hilt ,  Albert A. Talin

IPC分类号： H01L031/109

CPC分类号： H01L21/31691 ,  H01L21/02197 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521

摘要： Process for fabricating a semiconductor structure (34), and the resulting products, having reduced crystal defects and/or contamination in a monocrystalline compound semiconductor layer (26) that is compliantly attached to a monocrystalline semiconductor substrate (22) via an accommodating buffer layer (36), a capping/template layer (30), and a thin monocrystalline compound semiconductor seed film (38) comprised of a compound semiconductor, in that order from furthest to closest to layer (26). To accomplish this, a thin monocrystalline compound semiconductor seed film (38) is formed on an intermediate structure (33) including a monocrystalline perovskite buffer layer (24) and an overlying capping/template layer (30), and the resulting structure (33) is annealed at a temperature effective to reduce crystal defects in the compound semiconductor seed film (38), and optionally also may be used to amorphize the monocrystalline perovskite layer, all before a compound semiconductor layer (26) is formed thereon in a device-thickness.

摘要翻译： 制造半导体结构（34）的方法以及所得产品具有通过容纳缓冲层顺应地附接到单晶半导体衬底（22）的单晶化合物半导体层（26）中具有减小的晶体缺陷和/或污染 36），封盖/模板层（30）和由化合物半导体构成的薄单晶化合物半导体种子膜（38），其从最远到最靠近层（26）的顺序。 为了实现这一点，在包括单晶钙钛矿缓冲层（24）和上覆盖/模板层（30）的中间结构（33）上形成薄单晶化合物半导体种子膜（38），所得结构（33） 在有效地减少化合物半导体种子膜（38）中的晶体缺陷的温度下进行退火，并且任选地还可以将其用于非晶化单晶钙钛矿层，所有这些都是在其上形成化合物半导体层（26）之前的器件厚度 。