公开(公告)号：US06960836B2

公开(公告)日：2005-11-01

申请号：US10675260

申请日：2003-09-30

申请人： Mark Adam Bachman ,  Daniel Patrick Chesire ,  Sailesh Mansinh Merchant ,  John William Osenbach ,  Kurt George Steiner

发明人： Mark Adam Bachman ,  Daniel Patrick Chesire ,  Sailesh Mansinh Merchant ,  John William Osenbach ,  Kurt George Steiner

IPC分类号： H01L21/60 ,  H01L23/00 ,  H01L23/485 ,  H01L23/52

CPC分类号： H01L24/05 ,  H01L21/768 ,  H01L23/562 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05093 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/05552

摘要： Disclosed herein is a reinforcing system and method for reinforcing a contact pad of an integrated circuit. Specifically exemplified is a system and method that comprises a reinforcing structure interposed between a top contact pad layer and an underlying metal layer.

摘要翻译： 本文公开了一种用于加强集成电路的接触焊盘的增强系统和方法。 具体示出的是包括插入在顶部接触垫层和下面的金属层之间的加强结构的系统和方法。

公开(公告)号：US20090072393A1

公开(公告)日：2009-03-19

申请号：US11884328

申请日：2006-02-24

申请人： Mark Adam Bachman ,  Donald Stephen Bitting ,  Daniel Patrick Chesire ,  Taeho Kook ,  Sailesh Mansinh Merchant

发明人： Mark Adam Bachman ,  Donald Stephen Bitting ,  Daniel Patrick Chesire ,  Taeho Kook ,  Sailesh Mansinh Merchant

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad (200) disposed thereon. A passivation layer (202) overlies the upper surface. A second conductive pad (212) is disposed in an opening (204) in the passivation layer and in contact with the first conductive pad. The under bump metallurgical structure (300) encapsulates the second conductive pad, covering an upper surface and sidewalls surfaces of the second conductive pad, protecting both the first and the second conductive pads from environmental and processing effects. According to the present invention, the conventional second passivation layer is not required. Methods for forming the various structures are also presented.

摘要翻译： 焊料凸块结构和凹凸金属结构。 半导体衬底的上表面包括设置在其上的第一导电焊盘（200）。 钝化层（202）覆盖在上表面上。 第二导电焊盘（212）设置在钝化层中的开口（204）中并与第一导电焊盘接触。 凸块下金属结构（300）封装第二导电焊盘，覆盖第二导电焊盘的上表面和侧壁表面，保护第一和第二导电焊盘免受环境和处理的影响。 根据本发明，不需要传统的第二钝化层。 还提出了形成各种结构的方法。

公开(公告)号：US07328830B2

公开(公告)日：2008-02-12

申请号：US10741155

申请日：2003-12-19

申请人： Mark Adam Bachman ,  Daniel Patrick Chesire ,  Sailesh Mansinh Merchant

发明人： Mark Adam Bachman ,  Daniel Patrick Chesire ,  Sailesh Mansinh Merchant

IPC分类号： B23K31/02

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/32136 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11901 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8501 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure and a method for fabricating the structure. The method comprises forming a copper bond pad for attaching the integrated circuit to a package. Copper oxide is removed from the pad by reduction in a hydrogen ion atmosphere. For attaching the integrated circuit to a bump-bonding package an under-bump metallization layer is formed over the reduced copper pad and a solder bump formed thereover. The process can also be employed in a wire bonding process by forming an aluminum layer overlying the cleaned copper pad. The structure of the present invention comprises a copper pad formed in a substrate. A passivation layer defining an opening therein overlies the copper pad. A under-bump metallization layer is disposed in the opening and a solder bump overlies the metallization layer. Alternatively, the structure further comprises an aluminum pad disposed overlying the reduced copper pad.

摘要翻译： 集成电路结构及其制造方法。 该方法包括形成用于将集成电路附接到封装的铜焊盘。 通过在氢离子气氛中还原，将铜氧化物从垫中除去。 为了将集成电路连接到凸块焊接封装，在减小的铜焊盘上形成凸起下金属化层，并在其上形成焊料凸块。 该方法也可以通过形成覆盖在清洁的铜垫上的铝层在引线接合工艺中使用。 本发明的结构包括形成在基板中的铜焊盘。 限定其中的开口的钝化层覆盖在铜焊盘上。 凸起下金属化层设置在开口中，并且焊料凸块覆盖在金属化层上。 或者，该结构还包括设置在还原铜垫上的铝垫。

公开(公告)号：US07777333B2

公开(公告)日：2010-08-17

申请号：US11884328

申请日：2006-02-24

申请人： Mark Adam Bachman ,  Donald Stephen Bitting ,  Daniel Patrick Chesire ,  Taeho Kook ,  Sailesh Mansinh Merchant

发明人： Mark Adam Bachman ,  Donald Stephen Bitting ,  Daniel Patrick Chesire ,  Taeho Kook ,  Sailesh Mansinh Merchant

IPC分类号： H01L23/488

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad (200) disposed thereon. A passivation layer (202) overlies the upper surface. A second conductive pad (212) is disposed in an opening (204) in the passivation layer and in contact with the first conductive pad. The under bump metallurgical structure (300) encapsulates the second conductive pad, covering an upper surface and sidewalls surfaces of the second conductive pad, protecting both the first and the second conductive pads from environmental and processing effects. According to the present invention, the conventional second passivation layer is not required. Methods for forming the various structures are also presented.

摘要翻译： 焊料凸块结构和凹凸金属结构。 半导体衬底的上表面包括设置在其上的第一导电焊盘（200）。 钝化层（202）覆盖在上表面上。 第二导电焊盘（212）设置在钝化层中的开口（204）中并与第一导电焊盘接触。 凸块下金属结构（300）封装第二导电焊盘，覆盖第二导电焊盘的上表面和侧壁表面，保护第一和第二导电焊盘免受环境和处理的影响。 根据本发明，不需要传统的第二钝化层。 还提出了形成各种结构的方法。

公开(公告)号：US07566964B2

公开(公告)日：2009-07-28

申请号：US10675258

申请日：2003-09-30

申请人： Seung H. Kang ,  Roland P. Krebs ,  Kurt George Steiner ,  Michael C. Ayukawa ,  Sailesh Mansinh Merchant

发明人： Seung H. Kang ,  Roland P. Krebs ,  Kurt George Steiner ,  Michael C. Ayukawa ,  Sailesh Mansinh Merchant

IPC分类号： H01L23/52

CPC分类号： H01L23/5286 ,  H01L23/53214 ,  H01L23/53228 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit device structure and a process for fabricating the structure wherein the power bus interconnect structure is formed in the aluminum pad or contact layer. An interconnect structure for interconnecting underlying levels of interconnect can also be formed in the aluminum pad layer.

摘要翻译： 集成电路器件结构和制造该结构的工艺，其中电源总线互连结构形成在铝焊盘或接触层中。 用于互连互连的下层的互连结构也可以形成在铝焊盘层中。

公开(公告)号：US07541238B2

公开(公告)日：2009-06-02

申请号：US11414902

申请日：2006-05-01

申请人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Kurt George Steiner ,  Susan Clay Vitkavage

发明人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Kurt George Steiner ,  Susan Clay Vitkavage

IPC分类号： H01L21/8238

CPC分类号： H01L24/10 ,  H01F41/041 ,  H01L23/5227 ,  H01L24/13 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10T29/4902 ,  H01L2924/00 ,  H01L2224/48

摘要： An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.

摘要翻译： 在集成电路内形成的电感器和形成电感器的方法。 该电感器包括形成在第一金属化层中并被图案化并蚀刻成所需形状的铝的下层。 在一个实施例中，铝线包括螺旋形状。 根据镶嵌工艺，在覆盖铝线并且与其电接触的介电层中形成优选铜的导电流道。 铝线和导电流道配合形成电感器。 在另一个实施例中，铝线和导电流道以垂直间隔的方向形成，其中形成钨塞或导电通孔以提供电连接。 形成电感器的方法包括形成铝导线并在导线上形成导电流道。

公开(公告)号：US20090100668A1

公开(公告)日：2009-04-23

申请号：US12340813

申请日：2008-12-22

申请人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Kurt George Steiner ,  Susan Clay Vitkavage

发明人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Kurt George Steiner ,  Susan Clay Vitkavage

IPC分类号： H01F41/00

CPC分类号： H01L24/10 ,  H01F41/041 ,  H01L23/5227 ,  H01L24/13 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10T29/4902 ,  H01L2924/00 ,  H01L2224/48

摘要： An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.

摘要翻译： 在集成电路内形成的电感器和形成电感器的方法。 该电感器包括形成在第一金属化层中并被图案化并蚀刻成所需形状的铝的下层。 在一个实施例中，铝线包括螺旋形状。 根据镶嵌工艺，在覆盖铝线并且与其电接触的介电层中形成优选铜的导电流道。 铝线和导电流道配合形成电感器。 在另一个实施例中，铝线和导电流道以垂直间隔的方向形成，其中形成钨塞或导电通孔以提供电连接。 形成电感器的方法包括形成铝导线并在导线上形成导电流道。

公开(公告)号：US07068139B2

公开(公告)日：2006-06-27

申请号：US10953475

申请日：2004-09-29

申请人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Kurt George Steiner ,  Susan Clay Vitkavage

发明人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Kurt George Steiner ,  Susan Clay Vitkavage

IPC分类号： H01F5/00

CPC分类号： H01L24/10 ,  H01F41/041 ,  H01L23/5227 ,  H01L24/13 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10T29/4902 ,  H01L2924/00 ,  H01L2224/48

摘要： An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.

公开(公告)号：US07678639B2

公开(公告)日：2010-03-16

申请号：US12340813

申请日：2008-12-22

申请人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Kurt George Steiner ,  Susan Clay Vitkavage

发明人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Kurt George Steiner ,  Susan Clay Vitkavage

IPC分类号： H01L21/8238

CPC分类号： H01L24/10 ,  H01F41/041 ,  H01L23/5227 ,  H01L24/13 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10T29/4902 ,  H01L2924/00 ,  H01L2224/48

摘要： An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.

摘要翻译： 在集成电路内形成的电感器和形成电感器的方法。 该电感器包括形成在第一金属化层中并被图案化并蚀刻成所需形状的铝的下层。 在一个实施例中，铝线包括螺旋形状。 根据镶嵌工艺，在覆盖铝线并且与其电接触的介电层中形成优选铜的导电流道。 铝线和导电流道配合形成电感器。 在另一个实施例中，铝线和导电流道以垂直间隔的方向形成，其中形成钨塞或导电通孔以提供电连接。 形成电感器的方法包括形成铝导线并在导线上形成导电流道。

公开(公告)号：US06869873B2

公开(公告)日：2005-03-22

申请号：US10609889

申请日：2003-06-30

申请人： Robert Wayne Bradshaw ,  Daniele Gilkes ,  Sailesh Mansinh Merchant ,  Deepak A. Ramappa ,  Kurt George Steiner

发明人： Robert Wayne Bradshaw ,  Daniele Gilkes ,  Sailesh Mansinh Merchant ,  Deepak A. Ramappa ,  Kurt George Steiner

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/538 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/528 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/00

摘要： A silane passivation process, carried out in-situ together with the formation of a subsequent dielectric film, converts the exposed Cu surfaces of a Cu interconnect structure, to copper silicide. The copper silicide suppresses Cu diffusion and electromigration and serves as a barrier material in regions where contact to further conductive material is made. An entire copper surface of a copper interconnect structure may be silicided or a local portion of the surface silicided after an opening is formed in an overlying dielectric to expose a portion of the copper surface.

摘要翻译： 与形成随后的电介质膜一起原位进行的硅烷钝化工艺将Cu互连结构的暴露的Cu表面转化为硅化铜。 铜硅化物抑制Cu扩散和电迁移，并在与其它导电材料接触的区域中用作阻挡材料。 铜互连结构的整个铜表面可以在覆盖电介质中形成开口以暴露铜表面的一部分之后被硅化或表面硅化的局部部分。