公开(公告)号：US20070069394A1

公开(公告)日：2007-03-29

申请号：US11459249

申请日：2006-07-21

申请人： Mark Bachman ,  Donald Bitting ,  Sailesh Chittipeddi ,  Seung Kang ,  Sailesh Merchant

发明人： Mark Bachman ,  Donald Bitting ,  Sailesh Chittipeddi ,  Seung Kang ,  Sailesh Merchant

IPC分类号： H01L23/48

CPC分类号： H01L24/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2224/05552

摘要： The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.

摘要翻译： 本发明在一个方面提供一种半导体器件，其包括位于半导体衬底之上的互连层。 钝化层位于互连层上并且具有形成在其中的焊料凸块支撑开口。 包括导电材料的支撑柱位于焊料凸块支撑开口内。

公开(公告)号：US20070063352A1

公开(公告)日：2007-03-22

申请号：US11469960

申请日：2006-09-05

申请人： Vance Archer ,  Michael Ayukawa ,  Mark Bachman ,  Daniel Chesire ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Kurt Steiner

发明人： Vance Archer ,  Michael Ayukawa ,  Mark Bachman ,  Daniel Chesire ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Kurt Steiner

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/013

摘要： The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.

摘要翻译： 本发明提供一种焊料凸块结构。 在一个方面，焊料凸块结构用于诸如集成电路的半导体器件中。 半导体器件包括位于半导体衬底之上的有源器件，包括形成在有源器件上的铜的互连层以及位于互连层上的最外层金属化层。 最外面的金属化层包括铝，并且包括至少一个接合焊盘和至少一个互连转子，每一个电连接到互连层。 凹凸金属化层（UBM）位于接合焊盘上方，焊料凸块位于UBM上方。

公开(公告)号：US20070069365A1

公开(公告)日：2007-03-29

申请号：US11237633

申请日：2005-09-28

申请人： Vance Archer ,  Daniel Chesire ,  Seung Kang ,  Taeho Kooh ,  Sailesh Merchant

发明人： Vance Archer ,  Daniel Chesire ,  Seung Kang ,  Taeho Kooh ,  Sailesh Merchant

IPC分类号： H01L23/12

CPC分类号： G01R31/2884

摘要： Disclosed herein are novel damage detection circuitries implemented on the periphery of a semiconductor device. The circuitries disclosed herein enable the easy identification of cracks and deformation, and other types of damage that commonly occur during test and assembly processes of semiconductor devices.

摘要翻译： 这里公开了在半导体器件的外围实现的新的损伤检测电路。 这里公开的电路使得能够容易地识别裂纹和变形以及在半导体器件的测试和组装过程中通常发生的其它类型的损坏。

公开(公告)号：US20080026508A1

公开(公告)日：2008-01-31

申请号：US11868624

申请日：2007-10-08

申请人： Vance Archer ,  Kouros Azimi ,  Daniel Chesire ,  Warren Gladden ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Vivian Ryan

发明人： Vance Archer ,  Kouros Azimi ,  Daniel Chesire ,  Warren Gladden ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Vivian Ryan

IPC分类号： H01L21/00

CPC分类号： H01L23/36 ,  H01L21/4871 ,  H01L25/165 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

摘要： An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

摘要翻译： 一种集成电路装置，其包括冶金结合以增强对散热器的热传导。 在半导体器件中，集成电路管芯的表面冶金地结合到散热器的表面。 在制造器件的示例性方法中，封装衬底的上表面包括内部区域和周边区域。 集成电路管芯位于衬底表面上，并且集成电路管芯的第一表面被放置成与封装衬底接触。 金属层形成在集成电路管芯的第二相对表面上。 预成型件定位在金属层上，并且散热器位于预制件上。 用预成型件形成接合层，将散热器冶金结合到集成电路管芯的第二表面。

公开(公告)号：US20070168818A1

公开(公告)日：2007-07-19

申请号：US11673714

申请日：2007-02-12

申请人： Seung Kang ,  Subramanian Karthikeyan ,  Sailesh Merchant ,  Lisa Mullin

发明人： Seung Kang ,  Subramanian Karthikeyan ,  Sailesh Merchant ,  Lisa Mullin

IPC分类号： G01R31/30 ,  G06F11/00

CPC分类号： G01R31/2877 ,  G01R31/2856

摘要： A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.

摘要翻译： 半导体测试装置包括具有用于施加电信号和测量测试电路的电参数的触点的测试电路。 半导体测试装置还包括整体形成的加热电路，其包括邻近测试电路定位的至少一个电路弯道，用于升高测试电路的一部分内的温度。

公开(公告)号：US20060066335A1

公开(公告)日：2006-03-30

申请号：US10952453

申请日：2004-09-28

申请人： Seung Kang ,  Subramanian Karthikeyan ,  Sailesh Merchant ,  Lisa Mullin

发明人： Seung Kang ,  Subramanian Karthikeyan ,  Sailesh Merchant ,  Lisa Mullin

IPC分类号： G01R31/02

CPC分类号： G01R31/2877 ,  G01R31/2856

摘要： A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.

摘要翻译： 半导体测试装置包括具有用于施加电信号和测量测试电路的电参数的触点的测试电路。 半导体测试装置还包括整体形成的加热电路，其包括邻近测试电路定位的至少一个电路弯道，用于升高测试电路的一部分内的温度。

公开(公告)号：US20070069368A1

公开(公告)日：2007-03-29

申请号：US11235920

申请日：2005-09-27

申请人： Vance Archer ,  Kouros Azimi ,  Daniel Chesire ,  Warren Gladden ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Vivian Ryan

发明人： Vance Archer ,  Kouros Azimi ,  Daniel Chesire ,  Warren Gladden ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Vivian Ryan

IPC分类号： H01L23/34

CPC分类号： H01L23/36 ,  H01L21/4871 ,  H01L25/165 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

摘要： An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

摘要翻译： 一种集成电路装置，其包括冶金结合以增强对散热器的热传导。 在半导体器件中，集成电路管芯的表面冶金地结合到散热器的表面。 在制造器件的示例性方法中，封装衬底的上表面包括内部区域和周边区域。 集成电路管芯位于衬底表面上，并且集成电路管芯的第一表面被放置成与封装衬底接触。 金属层形成在集成电路管芯的第二相对表面上。 预成型件定位在金属层上，并且散热器位于预制件上。 用预成型件形成接合层，将散热器冶金结合到集成电路管芯的第二表面。

公开(公告)号：US20060192584A1

公开(公告)日：2006-08-31

申请号：US11403750

申请日：2006-04-13

申请人： Seung Kang ,  Subramanian Karthikeyan ,  Sailesh Merchant

发明人： Seung Kang ,  Subramanian Karthikeyan ,  Sailesh Merchant

IPC分类号： G01R31/26

CPC分类号： G01R31/2877 ,  G01R31/2853 ,  G01R31/2856 ,  H01L22/32

摘要： Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151-156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121-126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.

摘要翻译： 提供了用于确定测试半导体器件（10）中的加热效应的方法和测试结构。 测试装置可以包括用于接受引起加热效应的电流的第一导电金属结构（15 SUB-15 6）。 测试装置还可以包括靠近第一导电结构的第二导电金属结构，用于响应于加热效应而获得电阻率变化。 电阻率变化表示由于加热效应引起的温度变化。

公开(公告)号：US20060066337A1

公开(公告)日：2006-03-30

申请号：US10953292

申请日：2004-09-29

申请人： Seung Kang ,  Subramanian Karthikeyan ,  Sailesh Merchant

发明人： Seung Kang ,  Subramanian Karthikeyan ,  Sailesh Merchant

IPC分类号： G01R31/26

CPC分类号： G01R31/2877 ,  G01R31/2853 ,  G01R31/2856 ,  H01L22/32

摘要： Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151-156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121-126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.

公开(公告)号：US08258812B2

公开(公告)日：2012-09-04

申请号：US13079068

申请日：2011-04-04

申请人： Lew Chua-Eoan ,  Matthew Nowak ,  Seung Kang

发明人： Lew Chua-Eoan ,  Matthew Nowak ,  Seung Kang

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： H03K19/17748 ,  G11C11/161 ,  G11C11/165 ,  H03K19/17736 ,  H03K19/1778

摘要： Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions.

摘要翻译： 公开了使用旋转转矩磁阻随机存取存储器（STT-MRAM）技术的软件可编程逻辑的系统，电路和方法。 磁隧道结（MTJ）存储元件可以形成输入平面和输出平面。 输入平面和输出平面可以耦合在一起，形成允许实现逻辑功能的复杂阵列。