公开(公告)号：US20070069368A1

公开(公告)日：2007-03-29

申请号：US11235920

申请日：2005-09-27

Applicant: Vance Archer ,  Kouros Azimi ,  Daniel Chesire ,  Warren Gladden ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Vivian Ryan

Inventor： Vance Archer ,  Kouros Azimi ,  Daniel Chesire ,  Warren Gladden ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Vivian Ryan

IPC: H01L23/34

CPC classification number: H01L23/36 ,  H01L21/4871 ,  H01L25/165 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Abstract translation: 一种集成电路装置，其包括冶金结合以增强对散热器的热传导。 在半导体器件中，集成电路管芯的表面冶金地结合到散热器的表面。 在制造器件的示例性方法中，封装衬底的上表面包括内部区域和周边区域。 集成电路管芯位于衬底表面上，并且集成电路管芯的第一表面被放置成与封装衬底接触。 金属层形成在集成电路管芯的第二相对表面上。 预成型件定位在金属层上，并且散热器位于预制件上。 用预成型件形成接合层，将散热器冶金结合到集成电路管芯的第二表面。

公开(公告)号：US20060066327A1

公开(公告)日：2006-03-30

申请号：US10953291

申请日：2004-09-29

Applicant: Mark Bachman ,  Daniel Chesire ,  Taeho Kook ,  Sailesh Merchant

Inventor： Mark Bachman ,  Daniel Chesire ,  Taeho Kook ,  Sailesh Merchant

IPC: G01R31/02

CPC classification number: H01L24/10 ,  H01L22/32 ,  H01L24/13 ,  H01L2224/0392 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An interface assembly (20) and method for testing a semiconductor wafer prior to performing a flip chip bumping process are provided. The interface assembly includes a flip chip bonding pad (24) having a region (28) for performing the bumping process. A test pad (22) is integrally constructed with the bonding pad and includes a probe region (26) for performing wafer-level testing prior to performing the bumping process. The integral construction of the bonding and testing pads avoids, for example, an introduction of propagation delays to test signals passing therethrough, thereby improving the accuracy and reliability of wafer test results.

Abstract translation: 提供了一种用于在执行倒装芯片碰撞处理之前测试半导体晶片的界面组件（20）和方法。 接口组件包括具有用于执行碰撞处理的区域（28）的倒装芯片焊盘（24）。 测试焊盘（22）与接合焊盘一体构成，并且包括用于在执行碰撞过程之前进行晶片级测试的探针区域（26）。 焊接和测试焊盘的整体结构避免了例如引入传播延迟来测试通过其的信号，从而提高了晶片测试结果的准确性和可靠性。

公开(公告)号：US20060065969A1

公开(公告)日：2006-03-30

申请号：US10955913

申请日：2004-09-30

Applicant: Joze Antol ,  Philip Seitzer ,  Daniel Chesire ,  Rafe Mengel ,  Vance Archer ,  Thomas Gans ,  Taeho Kook ,  Sailesh Merchant

Inventor： Joze Antol ,  Philip Seitzer ,  Daniel Chesire ,  Rafe Mengel ,  Vance Archer ,  Thomas Gans ,  Taeho Kook ,  Sailesh Merchant

IPC: H01L23/053

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00015

Abstract: Disclosed herein are novel support structures for pad reinforcement in conjunction with new bond pad designs for semiconductor devices. The new bond pad designs avoid the problems associated with probe testing by providing a probe region that is separate from a wire bond region. Separating the probe region 212 from the wire bond region 210 and forming the bond pad 211 over active circuitry has several advantages. By separating the probe region 212 from the wire bond region 210, the wire bond region 210 is not damaged by probe testing, allowing for more reliable wire bonds. Also, forming the bond pad 211 over active circuitry, including metal interconnect layers, allows the integrated circuit to be smaller.

Abstract translation: 这里公开了用于衬垫加强的新型支撑结构以及用于半导体器件的新的接合焊盘设计。 新的焊盘设计通过提供与引线键合区域分离的探针区域来避免与探针测试相关的问题。 将探针区域212与引线接合区域210分离并通过有源电路形成接合焊盘211具有若干优点。 通过将探针区域212与引线键合区域210分离，引线键合区域210不会被探针测试所损坏，从而允许更可靠的引线键合。 此外，在包括金属互连层的有源电路上形成接合焊盘211允许集成电路更小。

公开(公告)号：US20050068608A1

公开(公告)日：2005-03-31

申请号：US10675263

申请日：2003-09-30

Applicant: Timothy Campbell ,  Daniel Chesire ,  Kelly Hinckley ,  Gregory Head ,  Benu Patel

Inventor： Timothy Campbell ,  Daniel Chesire ,  Kelly Hinckley ,  Gregory Head ,  Benu Patel

IPC: B81B3/00 ,  B81C1/00 ,  C23F4/00 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/00 ,  G02B6/26 ,  H01L29/82

CPC classification number: C23F4/00 ,  B81C1/00595 ,  H01L21/32136

Abstract: A process for etching a sacrificial layer of a structure. The structure is exposed to a plasma derived from nitrogen trifluoride for etching the sacrificial layer. The process is selective in that it etches titanium-nitride and titanium but does not affect adjacent silicon dioxide or aluminum layers. Applications of the process include the formation of integrated circuit structures and MEMS structures.

Abstract translation: 蚀刻结构的牺牲层的方法。 该结构暴露于来自三氟化氮的等离子体，用于蚀刻牺牲层。 该方法是选择性的，因为其蚀刻氮化钛和钛，但不影响相邻的二氧化硅或铝层。 该方法的应用包括形成集成电路结构和MEMS结构。

公开(公告)号：US20080026508A1

公开(公告)日：2008-01-31

申请号：US11868624

申请日：2007-10-08

Applicant: Vance Archer ,  Kouros Azimi ,  Daniel Chesire ,  Warren Gladden ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Vivian Ryan

Inventor： Vance Archer ,  Kouros Azimi ,  Daniel Chesire ,  Warren Gladden ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Vivian Ryan

IPC: H01L21/00

CPC classification number: H01L23/36 ,  H01L21/4871 ,  H01L25/165 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Abstract translation: 一种集成电路装置，其包括冶金结合以增强对散热器的热传导。 在半导体器件中，集成电路管芯的表面冶金地结合到散热器的表面。 在制造器件的示例性方法中，封装衬底的上表面包括内部区域和周边区域。 集成电路管芯位于衬底表面上，并且集成电路管芯的第一表面被放置成与封装衬底接触。 金属层形成在集成电路管芯的第二相对表面上。 预成型件定位在金属层上，并且散热器位于预制件上。 用预成型件形成接合层，将散热器冶金结合到集成电路管芯的第二表面。

公开(公告)号：US20060226535A1

公开(公告)日：2006-10-12

申请号：US11448560

申请日：2006-06-07

Applicant: Joze Antol ,  Philip Seitzer ,  Daniel Chesire ,  Rafe Mengel ,  Vance Archer ,  Thomas Gans ,  Taeho Kook ,  Sailesh Merchant

Inventor： Joze Antol ,  Philip Seitzer ,  Daniel Chesire ,  Rafe Mengel ,  Vance Archer ,  Thomas Gans ,  Taeho Kook ,  Sailesh Merchant

IPC: H01L23/04

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00015

Abstract: Disclosed herein are novel support structures for pad reinforcement in conjunction with new bond pad designs for semiconductor devices. The new bond pad designs avoid the problems associated with probe testing by providing a probe region that is separate from a wire bond region. Separating the probe region 212 from the wire bond region 210 and forming the bond pad 211 over active circuitry has several advantages. By separating the probe region 212 from the wire bond region 210, the wire bond region 210 is not damaged by probe testing, allowing for more reliable wire bonds. Also, forming the bond pad 211 over active circuitry, including metal interconnect layers, allows the integrated circuit to be smaller.

公开(公告)号：US20070069365A1

公开(公告)日：2007-03-29

申请号：US11237633

申请日：2005-09-28

Applicant: Vance Archer ,  Daniel Chesire ,  Seung Kang ,  Taeho Kooh ,  Sailesh Merchant

Inventor： Vance Archer ,  Daniel Chesire ,  Seung Kang ,  Taeho Kooh ,  Sailesh Merchant

IPC: H01L23/12

CPC classification number: G01R31/2884

Abstract: Disclosed herein are novel damage detection circuitries implemented on the periphery of a semiconductor device. The circuitries disclosed herein enable the easy identification of cracks and deformation, and other types of damage that commonly occur during test and assembly processes of semiconductor devices.

Abstract translation: 这里公开了在半导体器件的外围实现的新的损伤检测电路。 这里公开的电路使得能够容易地识别裂纹和变形以及在半导体器件的测试和组装过程中通常发生的其它类型的损坏。

公开(公告)号：US20070063352A1

公开(公告)日：2007-03-22

申请号：US11469960

申请日：2006-09-05

Applicant: Vance Archer ,  Michael Ayukawa ,  Mark Bachman ,  Daniel Chesire ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Kurt Steiner

Inventor： Vance Archer ,  Michael Ayukawa ,  Mark Bachman ,  Daniel Chesire ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Kurt Steiner

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/013

Abstract: The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.

Abstract translation: 本发明提供一种焊料凸块结构。 在一个方面，焊料凸块结构用于诸如集成电路的半导体器件中。 半导体器件包括位于半导体衬底之上的有源器件，包括形成在有源器件上的铜的互连层以及位于互连层上的最外层金属化层。 最外面的金属化层包括铝，并且包括至少一个接合焊盘和至少一个互连转子，每一个电连接到互连层。 凹凸金属化层（UBM）位于接合焊盘上方，焊料凸块位于UBM上方。

公开(公告)号：US20060226553A1

公开(公告)日：2006-10-12

申请号：US11368780

申请日：2006-03-06

Applicant: Timothy Campbell ,  Daniel Chesire ,  Kelly Hinckley ,  Gregory Head ,  Benu Patel

Inventor： Timothy Campbell ,  Daniel Chesire ,  Kelly Hinckley ,  Gregory Head ,  Benu Patel

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: C23F4/00 ,  B81C1/00595 ,  H01L21/32136

Abstract: A process for etching a sacrificial layer of a structure. The structure is exposed to a plasma derived from nitrogen trifluoride for etching the sacrificial layer. The process is selective in that it etches titanium-nitride and titanium but does not affect adjacent silicon dioxide or aluminum layers. Applications of the process include the formation of integrated circuit structures and MEMS structures.

公开(公告)号：US20050067709A1

公开(公告)日：2005-03-31

申请号：US10675260

申请日：2003-09-30

Applicant: Mark Bachman ,  Daniel Chesire ,  Sailesh Merchant ,  John Osenbach ,  Kurt Steiner

Inventor： Mark Bachman ,  Daniel Chesire ,  Sailesh Merchant ,  John Osenbach ,  Kurt Steiner

IPC: H01L21/60 ,  H01L23/00 ,  H01L23/485 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L21/768 ,  H01L23/562 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05093 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/05552

Abstract: Disclosed herein is a reinforcing system and method for reinforcing a contact pad of an integrated circuit. Specifically exemplified is a system and method that comprises a reinforcing structure interposed between a top contact pad layer and an underlying metal layer.

Abstract translation: 本文公开了一种用于加强集成电路的接触焊盘的增强系统和方法。 具体示出的是包括插入在顶部接触垫层和下面的金属层之间的加强结构的系统和方法。