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公开(公告)号:US20130084658A1
公开(公告)日:2013-04-04
申请号:US13252816
申请日:2011-10-04
CPC分类号: H01L21/78 , H01L21/50 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/67 , H01L21/67092 , H01L21/67144 , H01L21/683 , H01L21/6836 , H01L23/3107 , H01L2221/68322 , H01L2221/68327 , H01L2221/6834 , H01L2221/68368 , H01L2221/68381 , H01L2924/0002 , H01L2924/00
摘要: In accordance with an embodiment of the present invention, a semiconductor device is manufactured by arranging a plurality of semiconductor devices on a frame with an adhesive foil. The plurality of semiconductor devices is attached to the adhesive foil. The plurality of semiconductor devices is removed from the frame with the adhesive foil using a carbon dioxide snow jet and/or a laser process.
摘要翻译: 根据本发明的实施例,通过在框架上配置多个半导体器件来制造半导体器件,所述半导体器件具有粘合箔。 多个半导体器件附接到粘合箔。 使用二氧化碳喷射和/或激光工艺,使用粘合剂箔从框架中移除多个半导体器件。
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公开(公告)号:US08883565B2
公开(公告)日:2014-11-11
申请号:US13252816
申请日:2011-10-04
CPC分类号: H01L21/78 , H01L21/50 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/67 , H01L21/67092 , H01L21/67144 , H01L21/683 , H01L21/6836 , H01L23/3107 , H01L2221/68322 , H01L2221/68327 , H01L2221/6834 , H01L2221/68368 , H01L2221/68381 , H01L2924/0002 , H01L2924/00
摘要: In accordance with an embodiment of the present invention, a semiconductor device is manufactured by arranging a plurality of semiconductor devices on a frame with an adhesive foil. The plurality of semiconductor devices is attached to the adhesive foil. The plurality of semiconductor devices is removed from the frame with the adhesive foil using a carbon dioxide snow jet and/or a laser process.
摘要翻译: 根据本发明的实施例,通过在框架上配置多个半导体器件来制造半导体器件,所述半导体器件具有粘合箔。 多个半导体器件附接到粘合箔。 使用二氧化碳喷射和/或激光工艺,使用粘合剂箔从框架中移除多个半导体器件。
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公开(公告)号:US20130084659A1
公开(公告)日:2013-04-04
申请号:US13312758
申请日:2011-12-06
申请人: Stefan Martens , Mathias Vaupel
发明人: Stefan Martens , Mathias Vaupel
IPC分类号: H01L21/66
CPC分类号: H01L21/78 , H01L22/14 , H01L2224/97 , H01L2224/03
摘要: In accordance with an embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a wafer having a top surface and an opposite bottom surface. The top surface has a plurality of dicing channels. The wafer has a plurality of dies adjacent the top surface. Each die of the plurality of dies is separated by a dicing channel of the plurality of dicing channels from another die of the plurality of dies. Trenches are formed in the wafer from the top surface. The trenches are oriented along the plurality of dicing channels. After forming the trenches, the plurality of dies is tested to identify first dies to be separated from remaining dies of the plurality of dies. After testing the plurality of dies, the wafer is subjected to a grinding process from the back surface. The grinding process separates the wafer into the plurality of dies.
摘要翻译: 根据本发明的实施例,制造半导体器件的方法包括提供具有顶表面和相对底表面的晶片。 顶面具有多个切割通道。 晶片具有与顶表面相邻的多个模具。 多个管芯中的每个管芯由多个切割通道的切割通道与多个管芯中的另一管芯分开。 沟槽从顶表面形成在晶片中。 沟槽沿着多个切割通道定向。 在形成沟槽之后,测试多个管芯以识别与多个管芯的剩余管芯分离的第一管芯。 在测试多个模具之后,从背面对晶片进行研磨处理。 研磨过程将晶片分离成多个模具。
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公开(公告)号:US09099547B2
公开(公告)日:2015-08-04
申请号:US13312758
申请日:2011-12-06
申请人: Stefan Martens , Mathias Vaupel
发明人: Stefan Martens , Mathias Vaupel
CPC分类号: H01L21/78 , H01L22/14 , H01L2224/97 , H01L2224/03
摘要: In accordance with an embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a wafer having a top surface and an opposite bottom surface. The top surface has a plurality of dicing channels. The wafer has a plurality of dies adjacent the top surface. Each die of the plurality of dies is separated by a dicing channel of the plurality of dicing channels from another die of the plurality of dies. Trenches are formed in the wafer from the top surface. The trenches are oriented along the plurality of dicing channels. After forming the trenches, the plurality of dies is tested to identify first dies to be separated from remaining dies of the plurality of dies. After testing the plurality of dies, the wafer is subjected to a grinding process from the back surface. The grinding process separates the wafer into the plurality of dies.
摘要翻译: 根据本发明的实施例,制造半导体器件的方法包括提供具有顶表面和相对底表面的晶片。 顶面具有多个切割通道。 晶片具有与顶表面相邻的多个模具。 多个管芯中的每个管芯由多个切割通道的切割通道与多个管芯中的另一管芯分开。 沟槽从顶表面形成在晶片中。 沟槽沿着多个切割通道定向。 在形成沟槽之后,测试多个管芯以识别与多个管芯的剩余管芯分离的第一管芯。 在测试多个模具之后,从背面对晶片进行研磨处理。 研磨过程将晶片分离成多个模具。
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公开(公告)号:US08334202B2
公开(公告)日:2012-12-18
申请号:US12611609
申请日:2009-11-03
申请人: Jens Pohl , Hans-Joachim Barth , Gottfried Beer , Rainer Steiner , Werner Robl , Mathias Vaupel
发明人: Jens Pohl , Hans-Joachim Barth , Gottfried Beer , Rainer Steiner , Werner Robl , Mathias Vaupel
IPC分类号: H01L23/48
CPC分类号: H01L23/5389 , H01L21/486 , H01L21/76873 , H01L21/76879 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/82 , H01L24/97 , H01L2221/1089 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1461 , H01L2924/181 , H01L2224/82 , H01L2924/00
摘要: A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.
摘要翻译: 一种用于制造器件的方法包括提供包括至少一个接触的衬底并在衬底上施加电介质层。 该方法包括在电介质层上施加第一种子层,在种子层上施加惰性层,以及构造惰性层,第一种子层和电介质层以暴露至少一部分接触。 该方法包括在结构化介电层和触点的暴露部分上施加第二种子层,使得第二籽晶层与结构化的第一籽晶层电接触。 该方法包括在第二种子层上电镀金属。
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公开(公告)号:US20090108423A1
公开(公告)日:2009-04-30
申请号:US11924134
申请日:2007-10-25
IPC分类号: H01L23/495 , H01L21/02
CPC分类号: H01L23/3107 , H01L23/4334 , H01L23/49586 , H01L24/28 , H01L24/31 , H01L24/48 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01068 , H01L2924/01078 , H01L2924/078 , H01L2924/12044 , H01L2924/1306 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H05K3/3426 , H05K2201/10689 , H05K2203/124 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A semiconductor package includes a leadframe defining a die pad, a chip electrically coupled to the die pad, encapsulation material covering the chip and the die pad, and a plurality of lead ends exposed relative to the encapsulation material and configured for electrical communication with the chip, and a nitrogen-containing hydrocarbon coating disposed over at least the lead ends of the leadframe, where the hydrocarbon coating is free of metal particles.
摘要翻译: 半导体封装包括限定芯片焊盘的引线框架,电耦合到管芯焊盘的芯片,覆盖芯片和管芯焊盘的封装材料以及相对于封装材料暴露的多个引线端子,并被配置为与芯片电连通 ,以及设置在引线框架的至少引线端上的含氮烃涂层,其中烃涂层不含金属颗粒。
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公开(公告)号:US20120181710A1
公开(公告)日:2012-07-19
申请号:US13006104
申请日:2011-01-13
申请人: Mathias Vaupel
发明人: Mathias Vaupel
CPC分类号: H01L23/49586 , H01L23/49513 , H01L24/26 , H01L24/83 , H01L2221/6834 , H01L2224/26145 , H01L2224/26175 , H01L2224/83 , H01L2924/01079 , H01L2924/12044 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要: A semiconductor chip includes a first main face and a second main face opposed to the first main face. Side faces connect the first and second main faces. The side faces are at least partially covered with an anti-EBO compound and/or a surface energy reducing compound.
摘要翻译: 半导体芯片包括与第一主面相对的第一主面和第二主面。 侧面连接第一和第二主面。 侧面至少部分地被抗EBO化合物和/或表面能降低化合物覆盖。
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公开(公告)号:US08592999B2
公开(公告)日:2013-11-26
申请号:US13006104
申请日:2011-01-13
申请人: Mathias Vaupel
发明人: Mathias Vaupel
IPC分类号: H01L23/29
CPC分类号: H01L23/49586 , H01L23/49513 , H01L24/26 , H01L24/83 , H01L2221/6834 , H01L2224/26145 , H01L2224/26175 , H01L2224/83 , H01L2924/01079 , H01L2924/12044 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要: A semiconductor chip includes a first main face and a second main face opposed to the first main face. Side faces connect the first and second main faces. The side faces are at least partially covered with an anti-EBO compound and/or a surface energy reducing compound.
摘要翻译: 半导体芯片包括与第一主面相对的第一主面和第二主面。 侧面连接第一和第二主面。 侧面至少部分地被抗EBO化合物和/或表面能降低化合物覆盖。
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公开(公告)号:US07989930B2
公开(公告)日:2011-08-02
申请号:US11924134
申请日:2007-10-25
IPC分类号: H01L21/00
CPC分类号: H01L23/3107 , H01L23/4334 , H01L23/49586 , H01L24/28 , H01L24/31 , H01L24/48 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01068 , H01L2924/01078 , H01L2924/078 , H01L2924/12044 , H01L2924/1306 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H05K3/3426 , H05K2201/10689 , H05K2203/124 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A semiconductor package includes a leadframe defining a die pad, a chip electrically coupled to the die pad, encapsulation material covering the chip and the die pad, and a plurality of lead ends exposed relative to the encapsulation material and configured for electrical communication with the chip, and a nitrogen-containing hydrocarbon coating disposed over at least the lead ends of the leadframe, where the hydrocarbon coating is free of metal particles.
摘要翻译: 半导体封装包括限定芯片焊盘的引线框架,电耦合到管芯焊盘的芯片,覆盖芯片和管芯焊盘的封装材料以及相对于封装材料暴露的多个引线端子,并被配置为与芯片电连通 ,以及设置在引线框架的至少引线端上的含氮烃涂层,其中烃涂层不含金属颗粒。
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公开(公告)号:US08330274B2
公开(公告)日:2012-12-11
申请号:US12893009
申请日:2010-09-29
申请人: Hans-Joachim Barth , Gottfried Beer , Joern Plagmann , Jens Pohl , Werner Robl , Rainer Steiner , Mathias Vaupel
发明人: Hans-Joachim Barth , Gottfried Beer , Joern Plagmann , Jens Pohl , Werner Robl , Rainer Steiner , Mathias Vaupel
IPC分类号: H01L23/48
CPC分类号: H01L21/76843 , H01L21/76807 , H01L21/76879 , H01L23/49816 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L24/03 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01037 , H01L2924/01042 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/0106 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15788 , H01L2924/00
摘要: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
摘要翻译: 一个或多个实施例涉及一种形成半导体结构的方法,包括:提供工件; 在工件上形成阻挡层; 在阻挡层上形成种子层; 在种子层上形成抑制层; 去除所述抑制剂层的一部分以暴露所述种子层的一部分; 并且在曝光的种子层上选择性地沉积填充层。
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