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    Stress-reduced layer system for use in storage capacitors
    1.
    发明授权
    Stress-reduced layer system for use in storage capacitors 失效
    用于存储电容器的应力降低层系统

    公开(公告)号：US07199414B2

    公开(公告)日：2007-04-03

    申请号：US10780075

    申请日：2004-02-17

    申请人： Matthias Goldbach ,  Bernhard Sell ,  Annette Sänger

    发明人： Matthias Goldbach ,  Bernhard Sell ,  Annette Sänger

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/1087 ,  H01L27/10852 ,  H01L27/10861

    摘要： The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.

    摘要翻译： 应力降低层系统具有至少一个第一层多晶或单晶半导体材料，其邻接微晶或非晶，导电或绝缘的第二层。 半导体层掺杂有至少两种相同导电类型的掺杂剂，其中至少一种适用于降低界面处的机械应力。 在另一实施例中，应力降低层系统具有至少一个第一半导体材料层，导电或绝缘材料以及至少一个导电或绝缘的第二层。 掺杂有至少一种适合于在第二层和第一层之间的界面处降低机械应力的掺杂剂的另一半导体层被布置在第一层和第二层之间，或者被施加到 与界面相对的第一层或第二层。

    Method for the production of a self-adjusted structure on a semiconductor wafer
    2.
    发明授权
    Method for the production of a self-adjusted structure on a semiconductor wafer 失效
    在半导体晶片上制造自调整结构的方法

    公开(公告)号：US07041568B2

    公开(公告)日：2006-05-09

    申请号：US10485307

    申请日：2002-07-18

    申请人： Matthias Goldbach ,  Thomas Hecht ,  Jörn Lützen ,  Bernhard Sell

    发明人： Matthias Goldbach ,  Thomas Hecht ,  Jörn Lützen ,  Bernhard Sell

    IPC分类号： H01L21/20

    CPC分类号： H01L27/10867 ,  H01L21/0274

    摘要： A structure on a layer surface of the semiconductor wafer has at least one first area region (8, 9), which is reflective for electromagnetic radiation, and at least one second, essentially nonreflecting area region (10, 11, 12). A light-transmissive insulation layer (13) and a light-sensitive layer are produced on said layer surface. The electromagnetic radiation is directed onto the light-sensitive layer with an angle Θ of incidence and the structure of the layer surface is imaged with a lateral offset into the light-sensitive layer.

    摘要翻译： 半导体晶片的层表面上的结构具有至少一个反射用于电磁辐射的第一区域区域（8,9）和至少一个第二基本上不反射区域区域（10,11,12）。 在所述层表面上产生透光绝缘层（13）和感光层。 将电磁辐射以角度引导到感光层上。入射角和层表面的结构以横向偏移成像到感光层中。

    Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell
    3.
    发明授权
    Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell 失效
    用于读出，评估和再次读取电荷状态到存储单元中的电路布置

    公开(公告)号：US07009900B2

    公开(公告)日：2006-03-07

    申请号：US10944536

    申请日：2004-09-17

    申请人： Matthias Goldbach ,  Bernhard Sell

    发明人： Matthias Goldbach ,  Bernhard Sell

    IPC分类号： G11C7/00

    CPC分类号： G11C7/062 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/41 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50

    摘要： A circuit arrangement includes a bit line (10), a reference bit line (12), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor (20, 22) and a p-channel field-effect transistor (30, 32), and also, at the respective source terminals, two voltage sources (40, 42), of which the voltage source (40) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source (42) linked to the p-channel field-effect transistors (30, 32) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell (4) on the bit line (10) if the threshold voltages (UTH1, UTH2) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell (4).

    摘要翻译： 电路装置包括位线（10），参考位线（12），具有两个交叉耦合CMOS反相器的读出放大器，其在每种情况下都包括n沟道晶体管（20,22）和p沟道 场效应晶体管（30,32），并且在相应的源极端处，两个电压源（40,42），其中连接到n沟道场效应晶体管的电压源（40）可以从 连接到p沟道场效应晶体管（30,32）的电压源（42）可以从上到下的电位驱动。 利用这种电路装置，如果阈值电压（U TH1，U2，...，TH2），则可以在位线（10）上的存储单元（4）中存储三种不同的电荷状态， SUB>）被选择为大于电压下限和下限之间的电压差的一半。 这可以通过生产工程来实现，或者例如通过改变衬底偏置电压来实现。 第三充电状态可用于二进制逻辑或用于检测存储器单元（4）中的缺陷。

    Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell
    4.
    发明申请
    Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell 失效
    用于读出，评估和再次读取电荷状态到存储单元中的电路布置

    公开(公告)号：US20050099879A1

    公开(公告)日：2005-05-12

    申请号：US10944536

    申请日：2004-09-17

    申请人： Matthias Goldbach ,  Bernhard Sell

    发明人： Matthias Goldbach ,  Bernhard Sell

    IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50 ,  G11C8/02

    CPC分类号： G11C7/062 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/41 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50

    摘要： A circuit arrangement includes a bit line (10), a reference bit line (12), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor (20, 22) and a p-channel field-effect transistor (30, 32), and also, at the respective source terminals, two voltage sources (40, 42), of which the voltage source (40) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source (42) linked to the p-channel field-effect transistors (30, 32) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell (4) on the bit line (10) if the threshold voltages (UTH1, UTH2) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell (4).

    摘要翻译： 电路装置包括位线（10），参考位线（12），具有两个交叉耦合CMOS反相器的读出放大器，其在每种情况下都包括n沟道晶体管（20,22）和p沟道 场效应晶体管（30,32），并且在相应的源极端处，两个电压源（40,42），其中连接到n沟道场效应晶体管的电压源（40）可以从 连接到p沟道场效应晶体管（30,32）的电压源（42）可以从上到下的电位驱动。 利用这种电路装置，如果阈值电压（U TH1，U2，...，TH2），则可以在位线（10）上的存储单元（4）中存储三种不同的电荷状态， SUB>）被选择为大于电压下限和下限之间的电压差的一半。 这可以通过生产工程来实现，或者例如通过改变衬底偏置电压来实现。 第三充电状态可用于二进制逻辑或用于检测存储器单元（4）中的缺陷。

    Method for producing and/or renewing an etching mask
    6.
    发明授权
    Method for producing and/or renewing an etching mask 失效
    用于制造和/或更新蚀刻掩模的方法

    公开(公告)号：US06806037B2

    公开(公告)日：2004-10-19

    申请号：US10167785

    申请日：2002-06-12

    申请人： Matthias Goldbach ,  Thomas Hecht ,  Bernhard Sell

    发明人： Matthias Goldbach ,  Thomas Hecht ,  Bernhard Sell

    IPC分类号： G03F726

    CPC分类号： H01L21/3086 ,  H01L21/3081 ,  H01L21/3085

    摘要： An etching mask is produced for etching a substrate by a photoresist layer being exposed such that areas which are exposed once are not yet completely exposed and, on the basis of a reflective layer which is located under the photoresist layer, additionally exposed areas are exposed completely. In consequence, a first etching mask which is used for etching a substrate can be renewed by a second etching mask in that a photoresist layer which is applied to the first etching mask or instead of the first etching mask is exposed such that areas which have been exposed once are not yet completely exposed, and areas which have been additionally exposed on the basis of a reflective layer which is located under the photoresist layer and corresponds to the first etching mask are exposed completely.

    摘要翻译： 制造用于通过曝光的光致抗蚀剂层蚀刻基板的蚀刻掩模，使得暴露一次的区域尚未完全曝光，并且基于位于光致抗蚀剂层下方的反射层，额外暴露的区域完全暴露 。 因此，用于蚀刻衬底的第一蚀刻掩模可以通过第二蚀刻掩模来更新，因为施加到第一蚀刻掩模或代替第一蚀刻掩模的光致抗蚀剂层被暴露，使得已经被 曝光一次还未完全曝光，并且基于位于光致抗蚀剂层下方并对应于第一蚀刻掩模的反射层另外暴露的区域被完全暴露。

    Trench capacitor and method for manufacturing the same
    7.
    发明授权
    Trench capacitor and method for manufacturing the same 有权
    沟槽电容器及其制造方法

    公开(公告)号：US06674113B2

    公开(公告)日：2004-01-06

    申请号：US10254692

    申请日：2002-09-25

    申请人： Matthias Goldbach ,  Thomas Hecht ,  Jörn Lützen ,  Bernhard Sell

    发明人： Matthias Goldbach ,  Thomas Hecht ,  Jörn Lützen ,  Bernhard Sell

    IPC分类号： H01L2708

    CPC分类号： H01L27/10861

    摘要： A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first capacitor electrode has a tube-like structure, which extends into a substrate. The second capacitor electrode includes a first section which is opposite to the internal side of the tube-like structure, with the dielectric arranged therebetween, and a second section, which is opposite to the external side of the tube-like structure with the dielectric arranged therebetween.

    摘要翻译： 沟槽电容器具有布置在电容器电极之间的第一电容器电极，第二电容器电极和电介质。 第一电容器电极具有延伸到基板中的管状结构。 第二电容器电极包括与管状结构的内侧相对的第一部分，其间布置有电介质，第二部分与管状结构的外侧相反，电介质布置 之间。

    Method of removing refractory metal layers and of siliciding contact areas
    9.
    发明授权
    Method of removing refractory metal layers and of siliciding contact areas 失效
    去除难熔金属层和硅化接触区域的方法

    公开(公告)号：US07679149B2

    公开(公告)日：2010-03-16

    申请号：US11669500

    申请日：2007-01-31

    申请人： Audrey Beckert ,  Matthias Goldbach ,  Clemens Fitz

    发明人： Audrey Beckert ,  Matthias Goldbach ,  Clemens Fitz

    IPC分类号： H01L29/76

    CPC分类号： H01L21/28518 ,  H01L21/32134 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/66545 ,  H01L29/78

    摘要： A method of formation of contacts with cobalt silicide since is disclosed. For example, after siliciding with the SOM solution, both unreacted sections of the deposition layer including, for example, cobalt as initial layer for the siliciding and an oxidation protection layer including titanium and deposited by means of cathode beam sputtering, for instance, may be removed rapidly and with high selectivity relative to the cobalt silicide and other, densified metal structures and metal layers.

    摘要翻译： 公开了一种与硅化钴形成接触的方法。 例如，在用SOM溶液硅化后，例如包括例如作为硅化的初始层的钴的钴的沉积层的未反应部分和包括钛并通过阴极射线溅射沉积的氧化保护层可以是 相对于硅化钴和其它致密的金属结构和金属层，快速且高选择性地去除。