公开(公告)号：US5898207A

公开(公告)日：1999-04-27

申请号：US799211

申请日：1997-02-13

申请人： Michihiko Takase ,  Koji Eriguchi ,  Bunji Mizuno ,  Masatoshi Arai

发明人： Michihiko Takase ,  Koji Eriguchi ,  Bunji Mizuno ,  Masatoshi Arai

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/334 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L21/28211 ,  H01L28/40 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66181 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659

摘要： A semiconductor device with a damage-free insulating layer is fabricated. A method includes the steps of: forming a first insulating layer on a semiconductor substrate, forming a conductive layer on the first insulating layer, patterning the conductive layer to form a gate electrode, forming low-concentration source/drain region by a first ion implantation, removing a portion of the insulating layer positioned under the side end of the gate electrode, forming a second insulating layer over the semiconductor substrate, the second insulating layer is etched to form a sidewall, forming a high-concentration source/drain region by a second ion implantation.

摘要翻译： 制造具有无损绝缘层的半导体器件。 一种方法包括以下步骤：在半导体衬底上形成第一绝缘层，在第一绝缘层上形成导电层，图案化导电层以形成栅电极，通过第一离子注入形成低浓度源/漏区 去除位于栅电极侧端的绝缘层的一部分，在半导体衬底的上方形成第二绝缘层，蚀刻第二绝缘层以形成侧壁，形成高浓度源极/漏极区域 第二离子注入。

公开(公告)号：US5903031A

公开(公告)日：1999-05-11

申请号：US675659

申请日：1996-07-03

申请人： Takayuki Yamada ,  Takashi Nakabayashi ,  Masatoshi Arai ,  Toshiki Yabu ,  Koji Eriguchi

发明人： Takayuki Yamada ,  Takashi Nakabayashi ,  Masatoshi Arai ,  Toshiki Yabu ,  Koji Eriguchi

IPC分类号： H01L21/3213 ,  H01L21/768 ,  H01L29/78

CPC分类号： H01L21/76838 ,  H01L21/32136

摘要： In a first region of a semiconductor substrate, there are formed MIS transistors each composed of a gate insulating film, a gate electrode, and source/drain regions. In a second region of the semiconductor substrate, there is formed an impurity diffusion layer serving as a conductive layer. On an interlayer insulating film, there are formed an antenna interconnection connected to the gate electrodes and an interconnection for charge dissipation connected to the conductive layer. During the process of dry etching for forming the interconnections, charges move into the semiconductor substrate via the interconnection for charge dissipation. The deterioration of the gate insulating film caused by the injection of charges into the gate electrode is suppressed and the degradation of characteristics of the MIS transistor including a shift in threshold is also suppressed. Even in the case where a floating interconnection region is present contiguously to the antenna interconnection, the provision of the interconnection for charge dissipation reduces the amount of shift in the threshold of each of the MIS transistors and equalizes the respective thresholds of the MIS transistors.

摘要翻译： 在半导体基板的第一区域中，形成有由栅极绝缘膜，栅极电极和源极/漏极区域构成的MIS晶体管。 在半导体衬底的第二区域中，形成用作导电层的杂质扩散层。 在层间绝缘膜上形成连接到栅电极的天线布线和连接到导电层的用于电荷耗散的互连。 在用于形成互连的干蚀刻过程中，电荷通过互连进入半导体衬底以进行电荷耗散。 抑制了通过向栅电极注入电荷而导致的栅极绝缘膜的劣化，并且也抑制了包括阈值偏移的MIS晶体管的特性劣化。 即使在浮动互连区域与天线互连连续地存在的情况下，提供用于电荷耗散的互连减少了每个MIS晶体管的阈值偏移量，并且均衡了MIS晶体管的各个阈值。

公开(公告)号：US20070108614A1

公开(公告)日：2007-05-17

申请号：US11620976

申请日：2007-01-08

申请人： Koji Eriguchi ,  Susumu Matsumoto

发明人： Koji Eriguchi ,  Susumu Matsumoto

IPC分类号： H01L23/48

CPC分类号： H01L21/76838

摘要： At least a laminate of a gate insulating film 6 and a gate electrode 7 and an active region 13 are formed on a silicon substrate 1, and an underlying interlayer insulating film 10 is further formed. Then, a conductor 11a connected to the gate electrode 7, and a conductor 11b that is a dummy conductor and is connected to the active region 13 are formed simultaneously on the underlying interlayer insulating film 10. Thereafter, an interlayer insulating film 12 is formed on the underlying interlayer insulating film 10 by a plasma process. At this time, charging current from a plasma 14 is emitted through the conductor 11b, which is a dummy conductor.

摘要翻译： 至少在硅衬底1上形成栅极绝缘膜6和栅电极7以及有源区13的层叠体，并进一步形成下层层间绝缘膜10。 然后，在下面的层间绝缘膜10上同时形成连接到栅电极7的导体11a和作为虚拟导体并连接到有源区13的导体11b。 此后，通过等离子体处理在下层层间绝缘膜10上形成层间绝缘膜12。 此时，来自等离子体14的充电电流通过作为虚拟导体的导体11b发出。

公开(公告)号：US06720790B2

公开(公告)日：2004-04-13

申请号：US10385848

申请日：2003-03-12

申请人： Koji Eriguchi ,  Yukiko Hashimoto ,  Akio Watakabe

发明人： Koji Eriguchi ,  Yukiko Hashimoto ,  Akio Watakabe

IPC分类号： G01R3126

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a method for evaluating an insulating film entirely provided on a conductor layer for the characteristics or dimensions thereof. A measuring member having conductor bumps arranged thereon to be connected to wires is disposed above the insulating film on the conductor layer. Then, the conductor bumps are pressed against the insulating film with a given pressing force. By applying a voltage (electric stress) between the conductor bumps and the conductor layer, the characteristics including I-V characteristic, gate leakage current, and TDDB or the dimensions including thickness are evaluated.

摘要翻译： 提供了一种用于评价其特性或尺寸完全设置在导体层上的绝缘膜的方法。 在导体层上的绝缘膜的上方配置具有与导线连接的导体凸块的测定部件。 然后，以给定的按压力将导体凸块按压在绝缘膜上。 通过在导体凸块和导体层之间施加电压（电应力），评价包括I-V特性，栅极泄漏电流和TDDB的特性或包括厚度的尺寸。

公开(公告)号：US6087197A

公开(公告)日：2000-07-11

申请号：US227922

申请日：1999-01-08

申请人： Koji Eriguchi ,  Masafumi Kubota ,  Masaaki Niwa ,  Noboru Nomura

发明人： Koji Eriguchi ,  Masafumi Kubota ,  Masaaki Niwa ,  Noboru Nomura

IPC分类号： B81B3/00 ,  G01Q70/10 ,  G01Q70/16 ,  G02B6/12 ,  G02B6/124 ,  G11C23/00 ,  H01H1/00 ,  H01L21/308 ,  H01L31/0352 ,  H01L31/18 ,  H01L33/10 ,  H01L33/18 ,  H01L21/20

CPC分类号： H01L31/1804 ,  B82Y10/00 ,  G02B6/1245 ,  G11C23/00 ,  H01H1/0036 ,  H01L21/3086 ,  H01L31/0352 ,  G02B2006/12102 ,  G02B2006/12173 ,  G02B2006/12176 ,  H01L33/10 ,  H01L33/18 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S438/947 ,  Y10S438/962 ,  Y10S438/964

摘要： On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).

公开(公告)号：US6033928A

公开(公告)日：2000-03-07

申请号：US333320

申请日：1994-11-02

申请人： Koji Eriguchi ,  Masafumi Kubota ,  Masaaki Niwa ,  Noboru Nomura

发明人： Koji Eriguchi ,  Masafumi Kubota ,  Masaaki Niwa ,  Noboru Nomura

IPC分类号： B81B3/00 ,  G01Q70/10 ,  G01Q70/16 ,  G02B6/12 ,  G02B6/124 ,  G11C23/00 ,  H01H1/00 ,  H01L21/308 ,  H01L31/0352 ,  H01L31/18 ,  H01L33/10 ,  H01L33/18 ,  H01L21/32

CPC分类号： H01L31/1804 ,  B82Y10/00 ,  G02B6/1245 ,  G11C23/00 ,  H01H1/0036 ,  H01L21/3086 ,  H01L31/0352 ,  G02B2006/12102 ,  G02B2006/12173 ,  G02B2006/12176 ,  H01L33/10 ,  H01L33/18 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S438/947 ,  Y10S438/962 ,  Y10S438/964

摘要： On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).

摘要翻译： 在硅衬底上形成二氧化硅膜，然后通过LPCVD在其上沉积各自具有极小直径的由硅制成的半球状晶粒。 在半球形晶粒退火之后，使用半球形晶粒作为第一虚线掩模来蚀刻二氧化硅膜，由此形成由二氧化硅膜构成的第二虚线掩模。 所得到的第二点阵掩模用于将硅衬底从其表面蚀刻到指定的深度，从而形成半导体微针的聚集体。 由于每个半导体微针的直径足够小以致量子尺寸效应以及仅具有小的尺寸变化，因此可以获得显着的量子尺寸效应。 因此，通过使用半导体微针的集合体（量化区域），可以构成具有高信息处理功能的半导体装置。

公开(公告)号：US06974987B2

公开(公告)日：2005-12-13

申请号：US10477924

申请日：2003-02-14

申请人： Hisashi Ogawa ,  Isao Miyanaga ,  Koji Eriguchi ,  Takayuki Yamada ,  Kazuichiro Itonaga ,  Yoshihiro Mori

发明人： Hisashi Ogawa ,  Isao Miyanaga ,  Koji Eriguchi ,  Takayuki Yamada ,  Kazuichiro Itonaga ,  Yoshihiro Mori

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10882 ,  H01L27/10829 ,  H01L27/10894 ,  Y10S257/905 ,  Y10S257/908

摘要： A memory cell transistor and a trench capacitor are provided in a memory region, and both transistors of CMOS are provided in a logic circuit region. There are provided a bit line contact 31 and a bit line 32 extending on an inter-level dielectric 30. In a memory cell transistor, a source diffusion layer 18 is covered with two dielectric sidewalls 25a and 25b in the memory cell transistor so that no silicide layer is formed on the source diffusion layer 18. A plate contact 31 is provided to pass through the inter-level dielectric 30 and connect a shield line 33 to a plate electrode 16b. The shield line 33 is arranged in the same interconnect layer as the bit line 32.

摘要翻译： 存储单元晶体管和沟槽电容器设置在存储区域中，CMOS的两个晶体管都设置在逻辑电路区域中。 提供了位线接触件31和在层间电介质30上延伸的位线32。 在存储单元晶体管中，源极扩散层18被存储单元晶体管中的两个电介质侧壁25a和25b覆盖，使得在源极扩散层18上不形成硅化物层。 提供板触点31以通过层间电介质30并将屏蔽线33连接到平板电极16b。 屏蔽线33布置在与位线32相同的互连层中。

公开(公告)号：US06849470B1

公开(公告)日：2005-02-01

申请号：US09610640

申请日：2000-07-05

申请人： Koji Eriguchi ,  Takayuki Yamada ,  Masanori Okuyama

发明人： Koji Eriguchi ,  Takayuki Yamada ,  Masanori Okuyama

IPC分类号： H01L21/3065 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L21/3065

摘要： A top surface of a wafer is provided with an n-type source region, an n-type drain region, and an n-type semiconductor region. Dry etching using a plasma is performed with respect to an interlayer insulating film deposited on the wafer to form openings reaching the respective regions, followed by light etching for removing a damaged layer. In this case, exciting light is supplied intermittently to the n-type semiconductor region. The progression of the removal of the damaged layer and the stage of development of a newly damaged layer are sensed by monitoring the change rate of the intensity of reflected probe light in the presence and absence of the exciting light, resulting in the formation of a semiconductor device having low and equal contact resistance. In-line control using optical evaluation enables the implementation of semiconductor devices with excellent and consistent properties.

摘要翻译： 晶片的顶表面设置有n型源极区，n型漏极区和n型半导体区。 对沉积在晶片上的层间绝缘膜进行使用等离子体的干蚀刻，以形成到达各个区域的开口，然后进行光蚀刻以去除损伤层。 在这种情况下，向n型半导体区域间歇地供给激发光。 通过在存在和不存在激发光的情况下监测反射的探测光的强度的变化率来检测损坏层的去除进展和新损坏层的显影阶段，导致形成半导体 器件具有低和相等的接触电阻。 使用光学评估的在线控制使得能够实现具有优异和一致特性的半导体器件。

公开(公告)号：US20050006707A1

公开(公告)日：2005-01-13

申请号：US10859921

申请日：2004-06-02

申请人： Koji Eriguchi ,  Susumu Matsumoto

发明人： Koji Eriguchi ,  Susumu Matsumoto

IPC分类号： H01L21/768 ,  H01L29/76 ,  H01L21/4763

CPC分类号： H01L21/76838

摘要： At least a laminate of a gate insulating film 6 and a gate electrode 7 and an active region 13 are formed on a silicon substrate 1, and an underlying interlayer insulating film 10 is further formed. Then, a conductor 11a connected to the gate electrode 7, and a conductor 11b that is a dummy conductor and is connected to the active region 13 are formed simultaneously on the underlying interlayer insulating film 10. Thereafter, an interlayer insulating film 12 is formed on the underlying interlayer insulating film 10 by a plasma process. At this time, charging current from a plasma 14 is emitted through the conductor 11b, which is a dummy conductor.

摘要翻译： 至少在硅衬底1上形成栅极绝缘膜6和栅电极7以及有源区13的层叠体，并进一步形成下层层间绝缘膜10。 然后，在下面的层间绝缘膜10上同时形成连接到栅电极7的导体11a和作为虚拟导体并连接到有源区13的导体11b。之后，在层间绝缘膜12上形成层间绝缘膜12 通过等离子体处理的下层层间绝缘膜10。 此时，通过作为虚拟导体的导体11b发射来自等离子体14的充电电流。

公开(公告)号：US06727108B2

公开(公告)日：2004-04-27

申请号：US10461403

申请日：2003-06-16

申请人： Koji Eriguchi ,  Takayuki Yamada ,  Masanori Okuyama

发明人： Koji Eriguchi ,  Takayuki Yamada ,  Masanori Okuyama

IPC分类号： H01L2166

CPC分类号： H01L21/3065

摘要： A top surface of a wafer is provided with an n-type source region, an n-type drain region, and an n-type semiconductor region. Dry etching using a plasma is performed with respect to an interlayer insulating film deposited on the wafer to form openings reaching the respective regions, followed by light etching for removing a damaged layer. In this case, exciting light is supplied intermittently to the n-type semiconductor region. The progression of the removal of the damaged layer and the stage of development of a newly damaged layer are sensed by monitoring the change rate of the intensity of reflected probe light in the presence and absence of the exciting light, resulting in the formation of a semiconductor device having low and equal contact resistance. In-line control using optical evaluation enables the implementation of semiconductor devices with excellent and consistent properties.

摘要翻译： 晶片的顶表面设置有n型源极区，n型漏极区和n型半导体区。 对沉积在晶片上的层间绝缘膜进行使用等离子体的干蚀刻，以形成到达各个区域的开口，然后进行光蚀刻以去除损伤层。 在这种情况下，向n型半导体区域间歇地供给激发光。 通过在存在和不存在激发光的情况下监测反射的探测光的强度的变化率来检测损坏层的去除进展和新损坏层的显影阶段，导致形成半导体 器件具有低和相等的接触电阻。 使用光学评估的在线控制使得能够实现具有优异和一致特性的半导体器件。