Gallium nitride semiconductor device
    5.
    发明授权
    Gallium nitride semiconductor device 有权
    氮化镓半导体器件

    公开(公告)号:US07863172B2

    公开(公告)日:2011-01-04

    申请号:US12249099

    申请日:2008-10-10

    IPC分类号: H01L29/872 H01L29/47

    摘要: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

    摘要翻译: 由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层,其厚度介于1微米与6微米之间,设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。 优化了层厚度和细长指状物的长度和宽度,以实现具有大于500伏特的击穿电压,超过1安培的电流容量和小于3伏特的正向电压的器件。

    Gallium nitride semiconductor device
    6.
    发明授权
    Gallium nitride semiconductor device 失效
    氮化镓半导体器件

    公开(公告)号:US07436039B2

    公开(公告)日:2008-10-14

    申请号:US11030554

    申请日:2005-01-06

    IPC分类号: H01L23/58

    摘要: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

    摘要翻译: 由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层,其厚度介于1微米与6微米之间,设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。 优化了层厚度和细长指状物的长度和宽度,以实现具有大于500伏特的击穿电压,超过1安培的电流容量和小于3伏特的正向电压的器件。

    Gallium Nitride Semiconductor Device
    7.
    发明申请
    Gallium Nitride Semiconductor Device 有权
    氮化镓半导体器件

    公开(公告)号:US20090035925A1

    公开(公告)日:2009-02-05

    申请号:US12249099

    申请日:2008-10-10

    IPC分类号: H01L21/425

    摘要: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

    摘要翻译: 由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层,其厚度介于1微米与6微米之间,设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。 优化了层厚度和细长指状物的长度和宽度,以实现具有大于500伏特的击穿电压,超过1安培的电流容量和小于3伏特的正向电压的器件。

    Gallium nitride semiconductor
    8.
    发明申请
    Gallium nitride semiconductor 审中-公开
    氮化镓半导体

    公开(公告)号:US20110101371A1

    公开(公告)日:2011-05-05

    申请号:US12930179

    申请日:2010-12-30

    IPC分类号: H01L29/20

    摘要: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

    摘要翻译: 由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层,其厚度介于1微米与6微米之间,设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。 优化了层厚度和细长指状物的长度和宽度,以实现具有大于500伏特的击穿电压,超过1安培的电流容量和小于3伏特的正向电压的器件。

    Flip chip light emitting diode with micromesas and a conductive mesh
    10.
    发明授权
    Flip chip light emitting diode with micromesas and a conductive mesh 失效
    倒装芯片发光二极管,具有微电极和导电网

    公开(公告)号:US07064356B2

    公开(公告)日:2006-06-20

    申请号:US10826980

    申请日:2004-04-16

    IPC分类号: H01L33/00

    CPC分类号: H01L33/38 H01L33/08 H01L33/20

    摘要: A flip chip light emitting diode (12) includes a light-transmissive substrate (10) with a base semiconducting layer (40) disposed thereupon. A conductive mesh (18) is disposed on the base semiconducting layer (40) and is in electrically conductive contact therewith. Light-emitting micromesas (30) are disposed in openings (20) of the conductive mesh (18). Each light emitting micromesa (30) has a topmost layer (46) of a second conductivity type that is opposite the first conductivity type. A first conductivity type electrode (14) is disposed on the base semiconducting layer (40) and is in electrical communication with the electrically conductive mesh (18). An insulating layer (60) is disposed over the electrically conductive mesh (18). A second conductivity type electrode layer (24) is disposed over the insulating layer (60) and the light-emitting micromesas (30). the insulating layer (60) insulates the second conductivity type electrode layer (24) from the electrically conductive mesh (18).

    摘要翻译: 倒装芯片发光二极管(12)包括具有设置在其上的基极半导体层(40)的透光衬底(10)。 导电网(18)设置在基底半导体层(40)上并与其导电接触。 发光微镜(30)设置在导电网(18)的开口(20)中。 每个发光微镜(30)具有与第一导电类型相反的第二导电类型的最上层(46)。 第一导电型电极(14)设置在基底半导体层(40)上并与导电网(18)电连通。 绝缘层(60)设置在导电网(18)之上。 第二导电型电极层(24)设置在绝缘层(60)和发光微孔(30)之上。 绝缘层(60)将第二导电型电极层(24)与导电网(18)绝缘。