公开(公告)号：US20170133335A1

公开(公告)日：2017-05-11

申请号：US15336774

申请日：2016-10-27

申请人： NXP B.V.

发明人： Chi Ho Leung ,  Pompeo V. Umali ,  Shun Tik Yeung ,  Wai (Kan Wae) Lam

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48

CPC分类号： H01L24/05 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/562 ,  H01L24/03 ,  H01L25/0657 ,  H01L2224/03011 ,  H01L2224/03013 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/036 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05091 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/013

摘要： A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on the major surface and an encapsulant covering at least the major surface. A peripheral edge of each contact defines a contact area on the major surface. The device also includes one or more bond pads located outside the encapsulant. Each bond pad is electrically connected to a respective contact located on the major surface of the substrate by a respective metal filled via that passes through the encapsulant. A sidewall of each respective metal filled via, at the point at which it meets the respective contact, falls inside the contact area defined by the respective contact when viewed from above the major surface of the substrate, whereby none of the metal filling each respective via extends outside the contact area of each respective contact.

公开(公告)号：US20170053855A1

公开(公告)日：2017-02-23

申请号：US15229133

申请日：2016-08-05

申请人： NXP B.V.

发明人： KAN WAE LAM ,  Shun Tik Yeung ,  Pompeo V. Umali ,  Chi Ho Leung ,  Chi Ling Shum

IPC分类号： H01L23/495 ,  H01L21/78 ,  H01L21/56

CPC分类号： H01L23/49541 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49582 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

摘要： An electronic device has a first surface, a second surface opposite to the first surface, and sidewalls located between and adjoining the first and second surfaces. The electronic device includes contact pads on the first surface. The contact pads extend from the first surface to adjoining sidewalls, and abut the sidewalls.

摘要翻译： 电子设备具有第一表面，与第一表面相对的第二表面，以及位于第一表面和第二表面之间并与之相邻的侧壁。 电子设备包括第一表面上的接触垫。 接触焊盘从第一表面延伸到相邻的侧壁，并邻接侧壁。

公开(公告)号：US09391007B1

公开(公告)日：2016-07-12

申请号：US14746474

申请日：2015-06-22

申请人： NXP B.V.

发明人： Shun Tik Yeung ,  Pompeo V. Umali ,  Chi Ho Leung ,  Kan Wae Lam ,  Chi Ling Shum

IPC分类号： H01L21/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L25/00

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/544 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry. The semiconductor device includes a QFN package (quad-flat-pack no-leads) built-up substrate lead frame having, a sub-structure of I/O terminals and a die attach area, the I/O terminals and die attach area enveloped in a molding compound; the die attach area has exposed areas to facilitate device die attachment thereon and the terminal I/O terminals provide connection to the device die bond pads. I/O terminals are electrically coupled with one another and to the die attach area with connection traces. The coupled I/O terminals and connection traces facilitate electroplating of exposed vertical surfaces of the I/O terminals during assembly, said connection traces being severed after assembly. Molding compound encapsulates the device die on the built-up substrate lead frame. The exposed vertical surfaces of the I/O terminals enhance the solderability of the assembled QFN device during placement onto a printed circuit board.

摘要翻译： 与示例实施例一致，半导体器件包括具有提供到器件管芯电路的连接的接合焊盘的器件管芯。 半导体器件包括具有I / O端子的子结构和管芯附着区域的QFN封装（四扁平封装无引线）组合衬底引线框架，I / O端子和管芯附着区域被包围 在模塑料中; 管芯附接区域具有暴露区域以便于器件裸片附着在其上，并且端子I / O端子提供与器件管芯接合焊盘的连接。 I / O端子彼此电耦合，并连接到具有连接迹线的管芯附着区域。 耦合的I / O端子和连接迹线有助于在组装期间电镀I / O端子的暴露的垂直表面，所述连接迹线在组装之后被切断。 成型复合物将器件裸片封装在积层的基板引线框架上。 I / O端子的暴露的垂直表面增强了组装的QFN器件在放置到印刷电路板上时的可焊性。

公开(公告)号：US20160372403A1

公开(公告)日：2016-12-22

申请号：US14746612

申请日：2015-06-22

申请人： NXP B.V.

发明人： Kan Wae Lam ,  Pompeo V. Umali ,  Chi Ho Leung ,  Shun Tik Yeung ,  Chi Ling Shum

IPC分类号： H01L23/495 ,  H01L25/00 ,  H01L21/78 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L23/49503 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49861 ,  H01L23/544 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/50 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

摘要： Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry. The semiconductor device includes a built-up substrate lead frame having, a sub-structure of I/O terminals and a die attach area, the I/O terminals and die attach area enveloped in a molding compound, the die attach area having exposed areas to facilitate device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads; connection traces electrically couple the I/O terminals with one another, said connection traces having facilitated electroplating of exposed vertical surfaces of the I/O terminals during assembly, said connection traces being severed after assembly. An envelope of molding compound encapsulates the device die onto the built-up substrate lead frame.

摘要翻译： 与示例实施例一致，半导体器件包括具有提供到器件管芯电路的连接的接合焊盘的器件管芯。 半导体器件包括具有I / O端子的子结构和管芯附着区域的组合衬底引线框架，I / O端子和管芯附着区域包封在模制化合物中，管芯附着区域具有暴露区域 以便于其上的器件管芯附接和提供与器件管芯接合焊盘的连接的端子I / O端子; 连接迹线将I / O端子彼此电耦合，所述连接迹线在组装期间便于I / O端子的暴露的垂直表面的电镀，所述连接迹线在组装之后被切断。 模塑料的封套将器件裸片封装在组合的衬底引线框架上。