公开(公告)号：US08679952B2

公开(公告)日：2014-03-25

申请号：US13696943

申请日：2011-03-18

申请人： Nobuyuki Tomita ,  Kenichi Hamano ,  Masayoshi Tarutani ,  Yoichiro Mitani ,  Takeharu Kuroiwa ,  Masayuki Imaizumi ,  Hiroaki Sumitani ,  Kenichi Ohtsuka ,  Tomoaki Furusho ,  Takao Sawada ,  Yuji Abe

发明人： Nobuyuki Tomita ,  Kenichi Hamano ,  Masayoshi Tarutani ,  Yoichiro Mitani ,  Takeharu Kuroiwa ,  Masayuki Imaizumi ,  Hiroaki Sumitani ,  Kenichi Ohtsuka ,  Tomoaki Furusho ,  Takao Sawada ,  Yuji Abe

IPC分类号： H01L21/20

CPC分类号： H01L21/02529 ,  C30B25/02 ,  C30B25/186 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/6719 ,  H01L21/68771 ,  H01L29/1608

摘要： A method is provided in order to manufacture a silicon carbide epitaxial wafer whose surface flatness is very good and has a very low density of carrot defects and triangular defects arising after epitaxial growth. The silicon carbide epitaxial wafer is manufactured by a first step of annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from face, in a reducing gas atmosphere at a first temperature T1 for a treatment time t, a second step of reducing the temperature of the substrate in the reducing gas atmosphere, and a third step of performing epitaxial growth at a second temperature T2 below the annealing temperature T1 in the first step, while supplying at least a gas including silicon atoms and a gas including carbon atoms.

摘要翻译： 提供了一种方法来制造其表面平坦度非常好并且具有非常低的胡萝卜缺陷密度和外延生长后产生的三角形缺陷的碳化硅外延晶片。 碳化硅外延晶片是通过第一步骤，在还原气体气氛中，在第一温度T1处理处理时间t，退火碳化硅本体衬底，其从<0001>面倾斜小于5度;第二步骤 在第一步骤中，在低于退火温度T1的第二温度T2下进行外延生长的第三步骤，同时至少提供包含硅原子的气体和包括碳的气体 原子

公开(公告)号：US20130126906A1

公开(公告)日：2013-05-23

申请号：US13696943

申请日：2011-03-18

申请人： Nobuyuki Tomita ,  Kenichi Hamano ,  Masayoshi Tarutani ,  Yoichiro Mitani ,  Takeharu Kuroiwa ,  Masayuki Imaizumi ,  Hiroaki Sumitani ,  Kenichi Ohtsuka ,  Tomoaki Furusho ,  Takao Sawada ,  Yuji Abe

发明人： Nobuyuki Tomita ,  Kenichi Hamano ,  Masayoshi Tarutani ,  Yoichiro Mitani ,  Takeharu Kuroiwa ,  Masayuki Imaizumi ,  Hiroaki Sumitani ,  Kenichi Ohtsuka ,  Tomoaki Furusho ,  Takao Sawada ,  Yuji Abe

IPC分类号： H01L21/02 ,  H01L29/16

CPC分类号： H01L21/02529 ,  C30B25/02 ,  C30B25/186 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/6719 ,  H01L21/68771 ,  H01L29/1608

摘要： A method is provided in order to manufacture a silicon carbide epitaxial wafer whose surface flatness is very good and has a very low density of carrot defects and triangular defects arising after epitaxial growth. The silicon carbide epitaxial wafer is manufactured by a first step of annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from face, in a reducing gas atmosphere at a first temperature T1 for a treatment time t, a second step of reducing the temperature of the substrate in the reducing gas atmosphere, and a third step of performing epitaxial growth at a second temperature T2 below the annealing temperature T1 in the first step, while supplying at least a gas including silicon atoms and a gas including carbon atoms.

摘要翻译： 提供了一种方法来制造其表面平坦度非常好并且具有非常低的胡萝卜缺陷密度和外延生长后产生的三角形缺陷的碳化硅外延晶片。 碳化硅外延晶片是通过第一步骤，在还原气体气氛中，在第一温度T1处理处理时间t，退火碳化硅本体衬底，其从<0001>面倾斜小于5度;第二步骤 在第一步骤中，在低于退火温度T1的第二温度T2下进行外延生长的第三步骤，同时至少提供包含硅原子的气体和包括碳的气体 原子

公开(公告)号：US09093361B2

公开(公告)日：2015-07-28

申请号：US14116067

申请日：2012-03-07

申请人： Shiro Hino ,  Naruhisa Miura ,  Akihiko Furukawa ,  Yukiyasu Nakao ,  Tomokatsu Watanabe ,  Masayoshi Tarutani ,  Yuji Ebiike ,  Masayuki Imaizumi ,  Sunao Aya

发明人： Shiro Hino ,  Naruhisa Miura ,  Akihiko Furukawa ,  Yukiyasu Nakao ,  Tomokatsu Watanabe ,  Masayoshi Tarutani ,  Yuji Ebiike ,  Masayuki Imaizumi ,  Sunao Aya

IPC分类号： H01L29/76 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L21/04 ,  H01L29/417 ,  H01L29/06

CPC分类号： H01L29/1608 ,  H01L21/0485 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7816 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.

摘要翻译： 能够抑制阈值电压的时间变化的半导体器件及其制造方法。 根据本发明的半导体器件包括形成在半导体衬底上的漂移层，形成在漂移层的表面层中的第一阱区彼此分开，形成在栅极绝缘膜上的栅极绝缘膜，在漂移层上延伸，每个 选择性地形成在栅极绝缘膜上的栅极电极，穿过栅极绝缘膜并到达每个第一阱区域的内部的源极接触孔以及至少形成在第一阱区上的残留压应力层， 源接触孔的侧表面，其中保持压缩应力。

公开(公告)号：US20140077232A1

公开(公告)日：2014-03-20

申请号：US14116067

申请日：2012-03-07

申请人： Shiro Hino ,  Naruhisa Miura ,  Akihiko Furukawa ,  Yukiyasu Nakao ,  Tomokatsu Watanabe ,  Masayoshi Tarutani ,  Yuji Ebiike ,  Masayuki Imaizumi ,  Sunao Aya

发明人： Shiro Hino ,  Naruhisa Miura ,  Akihiko Furukawa ,  Yukiyasu Nakao ,  Tomokatsu Watanabe ,  Masayoshi Tarutani ,  Yuji Ebiike ,  Masayuki Imaizumi ,  Sunao Aya

IPC分类号： H01L29/16 ,  H01L29/78

CPC分类号： H01L29/1608 ,  H01L21/0485 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7816 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.

摘要翻译： 能够抑制阈值电压的时间变化的半导体器件及其制造方法。 根据本发明的半导体器件包括形成在半导体衬底上的漂移层，形成在漂移层的表面层中的第一阱区彼此分开，形成在栅极绝缘膜上的栅极绝缘膜，在漂移层上延伸，每个 选择性地形成在栅极绝缘膜上的栅极电极，穿过栅极绝缘膜并到达每个第一阱区域的内部的源极接触孔以及至少形成在第一阱区上的残留压应力层， 源接触孔的侧表面，其中保持压缩应力。

公开(公告)号：US09293572B2

公开(公告)日：2016-03-22

申请号：US13806534

申请日：2010-06-24

申请人： Akihiko Furukawa ,  Yasuhiro Kagawa ,  Naruhisa Miura ,  Shiro Hino ,  Shuhei Nakata ,  Kenichi Ohtsuka ,  Shoyu Watanabe ,  Masayuki Imaizumi

发明人： Akihiko Furukawa ,  Yasuhiro Kagawa ,  Naruhisa Miura ,  Shiro Hino ,  Shuhei Nakata ,  Kenichi Ohtsuka ,  Shoyu Watanabe ,  Masayuki Imaizumi

IPC分类号： H01L29/15 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/04 ,  H01L29/45

CPC分类号： H01L29/78 ,  H01L21/0485 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/45 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7805 ,  H01L29/7815

摘要： In a high speed switching power semiconductor device having a sense pad, a high voltage is generated during switching operations in well regions under the sense pad due to a displacement current flowing through its flow path with a resistance, whereby the power semiconductor device sometimes breaks down by dielectric breakdown of a thin insulating film such as a gate insulating film. In a power semiconductor device according to the invention, sense-pad well contact holes are provided on well regions positioned under the sense pad and penetrate a field insulating film thicker than the gate insulating film to connect to the source pad, thereby improving reliability.

摘要翻译： 在具有感测焊盘的高速开关电力半导体器件中，由于位移电流通过其流动路径而具有电阻，在感测焊盘下的阱区域的开关操作期间产生高电压，由此功率半导体器件有时会分解 通过诸如栅极绝缘膜的薄绝缘膜的电介质击穿。 在根据本发明的功率半导体器件中，感测焊盘井接触孔设置在位于感测焊盘下方的阱区上，并穿透比栅极绝缘膜更厚的场绝缘膜以连接到源极焊盘，从而提高可靠性。

公开(公告)号：US08680538B2

公开(公告)日：2014-03-25

申请号：US12867061

申请日：2008-02-12

申请人： Yoichiro Tarui ,  Kenichi Ohtsuka ,  Naruhisa Miura ,  Yoshinori Matsuno ,  Masayuki Imaizumi

发明人： Yoichiro Tarui ,  Kenichi Ohtsuka ,  Naruhisa Miura ,  Yoshinori Matsuno ,  Masayuki Imaizumi

IPC分类号： H01L29/15

CPC分类号： H01L29/66068 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/8613 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

摘要： In order to obtain a silicon carbide semiconductor device that ensures both stability of withstand voltage and reliability in high-temperature operations in its termination end-portion provided for electric-field relaxation in the perimeter of a cell portion driven as a semiconductor element, the termination end-portion is provided with an inorganic protection film having high heat resistance that is formed on an exposed surface of a well region as a first region formed on a side of the cell portion, and an organic protection film having a high electrical insulation capability with a little influence by electric charges that is formed on a surface of an electric-field relaxation region formed in contact relation to an outer lateral surface of the well region and apart from the cell portion, and on an exposed surface of the silicon carbide layer.

摘要翻译： 为了获得在作为半导体元件驱动的单元部分的周边中提供用于电场弛豫的其终端部分中的高温操作中的耐受电压的稳定性和可靠性的确保的碳化硅半导体器件， 端部设有具有高耐热性的无机保护膜，所述无机保护膜形成在作为形成在电池单元侧的第一区域的阱区的暴露表面上，以及具有高电绝缘能力的有机保护膜， 在形成于与阱区的外侧表面形成并且与电池部分隔开的电场弛豫区域的表面上以及在碳化硅层的暴露表面上的电荷的一点影响。

公开(公告)号：US20120074508A1

公开(公告)日：2012-03-29

申请号：US13309305

申请日：2011-12-01

申请人： Kenichi OHTSUKA ,  Naruhisa Miura ,  Masayuki Imaizumi ,  Tatsuo Oomori

发明人： Kenichi OHTSUKA ,  Naruhisa Miura ,  Masayuki Imaizumi ,  Tatsuo Oomori

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4941 ,  H01L29/66068 ,  H01L29/7828

摘要： A power semiconductor device less prone to cause a reaction between a metal material for interconnection and an electrode or the like connected to a semiconductor region during the high-temperature operation thereof and less prone to be strained during the high-temperature operation thereof. The power semiconductor device can be an SiC power device or the like in which a first metal layer containing at least one selected from the group consisting of Pt, Ti, Mo, W and Ta is formed on a source electrode formed on the semiconductor region, such as a source region or the like. A second metal layer containing at least one selected from the group consisting of Mo, W and Cu is formed on the first metal layer. A third metal layer containing at least one selected from the group consisting of Pt, Mo and W is formed on the second metal layer.

摘要翻译： 功率半导体器件在其高温操作期间不容易引起用于互连的金属材料与连接到半导体区域的电极等之间的反应，并且在其高温操作期间不易于变形。 功率半导体器件可以是在形成在半导体区域上的源电极上形成含有选自Pt，Ti，Mo，W和Ta中的至少一种的第一金属层的SiC功率器件等， 例如源区域等。 在第一金属层上形成含有选自Mo，W和Cu中的至少一种的第二金属层。 在第二金属层上形成含有选自Pt，Mo和W中的至少一种的第三金属层。

公开(公告)号：US20110001209A1

公开(公告)日：2011-01-06

申请号：US12867283

申请日：2009-03-12

申请人： Hiroshi Watanabe ,  Naoki Yutani ,  Kenichi Ohtsuka ,  Kenichi Kuroda ,  Masayuki Imaizumi ,  Yoshinori Matsuno

发明人： Hiroshi Watanabe ,  Naoki Yutani ,  Kenichi Ohtsuka ,  Kenichi Kuroda ,  Masayuki Imaizumi ,  Yoshinori Matsuno

IPC分类号： H01L29/47

CPC分类号： H01L29/872 ,  H01L21/0495 ,  H01L24/05 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage. A semiconductor device includes: an n− type semiconductor layer formed on an n+ type semiconductor substrate; a first electrode that is formed on the n− type semiconductor layer and functions as a Schottky electrode; a GR layer that is a first p type semiconductor layer formed on a surface of the n− type semiconductor layer below an end of the first electrode and a perimeter thereof; a JTE layer that is formed of a second p type semiconductor layer formed on a bottom and a lateral surface of a groove arranged in a ring shape around the GR layer apart from the GR layer, in a surface of the n− typesemiconductor layer; an insulating film provided so as to cover the GR layer and the JTE layer; and a second electrode that is an Ohmic electrode formed below a rear surface of the n+ type semiconductor substrate.

摘要翻译： 在提供JTE层的端接结构中，存在于半导体层和绝缘膜之间的界面处的水平或缺陷，或从绝缘膜或外部渗透到半导体界面的少量不定性杂质 通过绝缘膜成为漏电流的源极或击穿点，这会降低击穿电压。 半导体器件包括：形成在n +型半导体衬底上的n型半导体层; 形成在n型半导体层上并用作肖特基电极的第一电极; GR层，其是形成在所述第一电极的端部下方的所述n型半导体层的表面上的第一p型半导体层及其周边; 在所述n型半导体层的表面中形成由形成在所述GR层之外的围绕所述GR层的环状的槽的底部和侧面上形成的第二p型半导体层的JTE层; 设置为覆盖GR层和JTE层的绝缘膜; 以及形成在n +型半导体衬底的后表面下方的欧姆电极的第二电极。

公开(公告)号：US09006819B2

公开(公告)日：2015-04-14

申请号：US13639738

申请日：2011-02-08

申请人： Shiro Hino ,  Naruhisa Miura ,  Shuhei Nakata ,  Kenichi Ohtsuka ,  Shoyu Watanabe ,  Akihiko Furukawa ,  Yukiyasu Nakao ,  Masayuki Imaizumi

发明人： Shiro Hino ,  Naruhisa Miura ,  Shuhei Nakata ,  Kenichi Ohtsuka ,  Shoyu Watanabe ,  Akihiko Furukawa ,  Yukiyasu Nakao ,  Masayuki Imaizumi

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L29/861 ,  H01L29/06 ,  H01L29/16 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739

CPC分类号： H01L29/1095 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/42372 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7805 ,  H01L29/7811 ,  H01L29/8611

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底，形成在半导体衬底的第一主表面上的第一导电类型的漂移层，形成为围绕电池的第二导电类型的第二阱区域 漂移层的区域和用于通过设置成穿过第二阱区域上的栅极绝缘膜设置的第一阱接触孔电连接第二阱区域和电池区域的源极区域的源极焊盘，提供第二阱接触孔 以穿透第二阱区域上的场绝缘膜和源极接触孔。

公开(公告)号：US08304901B2

公开(公告)日：2012-11-06

申请号：US12867283

申请日：2009-03-12

申请人： Hiroshi Watanabe ,  Naoki Yutani ,  Kenichi Ohtsuka ,  Kenichi Kuroda ,  Masayuki Imaizumi ,  Yoshinori Matsuno

发明人： Hiroshi Watanabe ,  Naoki Yutani ,  Kenichi Ohtsuka ,  Kenichi Kuroda ,  Masayuki Imaizumi ,  Yoshinori Matsuno

IPC分类号： H01L23/48

CPC分类号： H01L29/872 ,  H01L21/0495 ,  H01L24/05 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage. A semiconductor device includes: an n− type semiconductor layer formed on an n+ type semiconductor substrate; a first electrode that is formed on the n− type semiconductor layer and functions as a Schottky electrode; a GR layer that is a first p type semiconductor layer formed on a surface of the n− type semiconductor layer below an end of the first electrode and a perimeter thereof; a JTE layer that is formed of a second p type semiconductor layer formed on a bottom and a lateral surface of a groove arranged in a ring shape around the GR layer apart from the GR layer, in a surface of the n− type semiconductor layer; an insulating film provided so as to cover the GR layer and the JTE layer; and a second electrode that is an Ohmic electrode formed below a rear surface of the n+ type semiconductor substrate.

摘要翻译： 在提供JTE层的端接结构中，存在于半导体层和绝缘膜之间的界面处的水平或缺陷，或从绝缘膜或外部渗透到半导体界面的少量不定性杂质 通过绝缘膜成为漏电流的源极或击穿点，这会降低击穿电压。 半导体器件包括：形成在n +型半导体衬底上的n型半导体层; 形成在n型半导体层上并用作肖特基电极的第一电极; GR层，其是形成在所述第一电极的端部下方的所述n型半导体层的表面上的第一p型半导体层及其周边; 在所述n型半导体层的表面中形成有由形成在所述GR层之外的与所述GR层相邻的所述GR层的环状的槽的底部和侧面上形成的第二p型半导体层的JTE层; 设置为覆盖GR层和JTE层的绝缘膜; 以及形成在n +型半导体衬底的后表面下方的欧姆电极的第二电极。