Substituted YiBa.sub.2 Cu.sub.3 oxide superconductor
    2.
    发明授权
    Substituted YiBa.sub.2 Cu.sub.3 oxide superconductor 失效
    取代YIBA2CU3氧化物超导体

    公开(公告)号:US5108986A

    公开(公告)日:1992-04-28

    申请号:US566317

    申请日:1990-08-13

    IPC分类号: H01L39/12 H01L39/24

    摘要: The invention relates to a superconductor manufacturing method and a superconductor manufactured by the method. More particularly, the invention is concerned wih an oxide superconductor of lamellar perovskite type and a method of manufacturing the same having extemely high critical temperature and critical current density as compared with conventional alloy superconductors or intermetallic compound superconductos. The superconductor is expressed byA-B-Cu-OwhereA represents at least one of elements of the group IIIa in the periodic table; andB represents at least one of elements of the group IIa in the periodic table,wherein at least one A and B consists of two elements belonging to the same group.The superconductor is manufactured by the steps of:(a) mixing powder of a compound containing at least one of elements of the group IIIa in the periodic table, powder of a compound containing at least one of elements of the group IIa in the periodic table, powder of a compound containing a homologous element of at least one of elements of the groups IIIa and IIa in the periodic table, and powder of copper oxide with each other in such a manner that a ratio in number of atoms among the at least one element of the group IIIa, the at least one element of the group IIa, Cu and O is brought to (0.1 to 2.0) : (0.1 to 3.0) : 1 : (1 to 4), to obtain raw material powder; and(b) sintering the raw material powder at a temperature in a range of from 800 to 1100 degrees C for 1 to 100 hours within an atmosphere in which oxygen concentration is at least 50%.

    Method for producing oxide superconducting composite wire
    4.
    发明授权
    Method for producing oxide superconducting composite wire 失效
    生产氧化物超导复合线的方法

    公开(公告)号:US5283232A

    公开(公告)日:1994-02-01

    申请号:US932933

    申请日:1992-08-20

    IPC分类号: H01L39/14 H01L39/24 H01B12/10

    摘要: A method for producing an oxide superconducting composite wire is disclosed, which comprises the steps of: (a) molding a powdered oxide superconductor material to form a wire; (b) heat treating the wire in an oxygen atmosphere thereby forming the wire into an oxide superconducting member; (c) forming a non-oxidizing metal intermediate layer on a surface of the oxide superconducting member; (d) bundling a plurality of the oxide superconducting members containing the intermediate layer; (e) inserting the bundled oxide superconducting members into an oxidizing metal support tube; and (f) drawing the product of step (e) to reduce its diameter and heat-treating it.

    摘要翻译: 公开了一种生产氧化物超导复合线材的方法,其包括以下步骤:(a)将粉末状氧化物超导体材料模制成线材; (b)在氧气氛中热处理所述线,由此将所述线形成为氧化物超导构件; (c)在所述氧化物超导构件的表面上形成非氧化性金属中间层; (d)将含有所述中间层的多个所述氧化物超导部件捆扎; (e)将所述捆扎的氧化物超导构件插入氧化金属支撑管中; 和(f)拉制步骤(e)的产品以减小其直径并对其进行热处理。

    Method of fabricating superconductive electrical conductor
    6.
    发明授权
    Method of fabricating superconductive electrical conductor 失效
    制造超导电导体的方法

    公开(公告)号:US4665611A

    公开(公告)日:1987-05-19

    申请号:US831462

    申请日:1986-02-19

    摘要: A method of fabricating a superconductive electrical conductor of Nb.sub.3 Sn type comprises a step of covering an elongated core member made of Nb with a covering member made of a third element selected from the group consisting of Ti, Ta, In, Hf, Al and Si. The core member covered with the covering member is covered with a tubular matrix made of a Cu-Sn alloy or a combination of Cu with Sn to form a composite wire element. Such wire elements are assembled in a tubular matrix made of a Cu-Sn alloy, Cu or a combination of Cu with Sn and reduced in diameter to form a multi-core composite wire element having a desired diameter. The assembling and reducing processing is effected at least one to form a multi-core composite wire which is then subjected to a diffusion heat-treatment to form an intermetallic compound of Nb.sub.3 Sn and the third element in the peripheral portion of the core member.

    摘要翻译: 制造Nb 3 Sn型超导电导体的方法包括用由Ti,Ta,In,Hf,Al和Si组成的组中选择的第三元素制成的覆盖部件覆盖由Nb制成的细长芯部件的步骤。 用覆盖部件覆盖的芯部件被由Cu-Sn合金或Cu与Sn的组合制成的管状基体覆盖以形成复合线元件。 这种线元件组装成由Cu-Sn合金制成的管状基体,Cu或Cu与Sn的组合并且直径减小以形成具有期望直径的多芯复合线材。 至少进行组装和还原处理以形成多芯复合线,然后进行扩散热处理以在芯构件的周边部分中形成Nb 3 Sn的金属间化合物和第三元素。

    Test circuit for evaluating characteristic of analog signal of device
    9.
    发明申请
    Test circuit for evaluating characteristic of analog signal of device 失效
    用于评估设备模拟信号特性的测试电路

    公开(公告)号:US20050179576A1

    公开(公告)日:2005-08-18

    申请号:US11048723

    申请日:2005-02-03

    摘要: In a test circuit, a determination circuit conducts a function test to determine whether timing of a slope section of waveform of an analog signal ANS of a measurement target device is within a range of specifications. An ADC performs AD-conversion only when a potential of analog signal ANS is within a range between reference potentials VOL, VOH. An analysis unit analyzes digital data from the ADC, and conducts a sloping waveform test to evaluate a sloping state of the waveform of analog signal ANS. Therefore, the slope section of the waveform of analog signal ANS of the device can be subjected to AD-conversion in a voltage range divided in arbitrary number of sections within a range of arbitrary voltage amplitude without requiring a large-capacity storage circuit. The function test by a determination circuit and the sloping waveform test by the analysis unit can be performed in parallel.

    摘要翻译: 在测试电路中,确定电路进行功能测试,以确定测量目标器件的模拟信号ANS的波形的斜率部分的定时是否在规格范围内。 只有当模拟信号ANS的电位在参考电位VOL,VOH之间的范围内时,ADC才执行AD转换。 分析单元从ADC分析数字数据,并进行倾斜波形测试,以评估模拟信号ANS波形的倾斜状态。 因此,可以在不需要大容量存储电路的情况下,在任意电压幅度的范围内,以任意数量的区间划分的装置的模拟信号ANS的波形的斜率部分进行AD转换。 可以并行地执行由判定电路进行的功能测试和分析单元的倾斜波形测试。

    LSI testing apparatus
    10.
    发明授权

    公开(公告)号:US06546525B2

    公开(公告)日:2003-04-08

    申请号:US09761179

    申请日:2001-01-18

    IPC分类号: G06F1750

    CPC分类号: G01R31/31908 G01R31/31922

    摘要: An LSI testing apparatus of the invention comprises: a plurality of pins P1, P2, . . . PN; function units 10, 11 and 12 which supply the pins with LSI testing signals, which have functions for making judgments on tests, and which are furnished for each of the pins; and clock mask function units 15A and 15B furnished on the input side of each function unit. Upon testing, any unused pin and function are detected so as to mask the clock mask function unit corresponding to the detected pin and function, whereby power dissipation is reduced in terms of unused pins and functions.