摘要:
Organic addition agents in copper plating baths are monitored by diluting a sample of the bath with sulfuric acid and hydrochloric acid and optionally a cupric salt. The diluting provides a bath having conventional concentrations of cupric ion, sulfuric acid and hydrochloric acid; and adjusted concentrations of the organic addition agents of 1/X of their original values in the sample; where X is the dilution factor. CVS techniques are used to determine concentrations of organic addition agents.
摘要:
Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 μm and via openings filled with electroplated copper than is substantially free of internal seams or voids.
摘要:
A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.
摘要:
A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
摘要:
An apparatus for monitoring and adding solution to a plating bath and controlling the quality of deposited metal. At least one monitor monitors at least one condition within a plating bath and produces at least one signal corresponding to the at least one condition. At least one controller receives the at least one signal produced by the at least one monitor, processes the at least one signal, determines whether an additional amount of at least one chemical should be added to the plating bath, and controls at least one valve for controlling flow of the additional amount of the at least one chemical. A pre-mix tank pre-mixes chemicals to be added to the tank. A plurality of holding tanks holds chemicals and supplies the chemicals to the pre-mix tank. At least one valve is arranged between each holding tank and the pre-mix tank. At least one valve is also arranged between the pre-mix tank and the plating bath.
摘要:
An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.
摘要:
An apparatus for monitoring and adding solution to a plating bath and controlling the quality of deposited metal. At least one monitor monitors at least one condition within a plating bath and produces at least one signal corresponding to the at least one condition. At least one controller receives the at least one signal produced by the at least one monitor, processes the at least one signal, determines whether an additional amount of at least one chemical should be added to the plating bath, and controls at least one valve for controlling flow of the additional amount of the at least one chemical. A pre-mix tank pre-mixes chemicals to be added to the tank. A plurality of holding tanks holds chemicals and supplies the chemicals to the pre-mix tank. At least one valve is arranged between each holding tank and the pre-mix tank. At least one valve is also arranged between the pre-mix tank and the plating bath.
摘要:
A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
摘要:
A method for forming metal interconnect in a semiconductor structure and the structure formed are disclosed. In the method, a seed layer of a first metal is first deposited into an interconnect opening wherein the seed layer has an average grain size of at least 0.0005 &mgr;m. The semiconductor structure is then annealed at a temperature sufficient to grow the average grain size in the seed layer to at least the film thickness. A filler layer of a second metal is then deposited to fill the interconnect opening overlaying the seed layer such that the filler layer has an average grain size of larger than 0.0005 &mgr;m and comparable to the annealed seed layer.
摘要:
A method for forming metal interconnect in a semiconductor structure and the structure formed are disclosed. In the method, a seed layer of a first metal is first deposited into an interconnect opening wherein the seed layer has an average grain size of at least 0.0005 &mgr;m. The semiconductor structure is then annealed at a temperature sufficient to grow the average grain size in the seed layer to at least the film thickness. A filler layer of a second metal is then deposited to fill the interconnect opening overlaying the seed layer such that the filler layer has an average grain size of larger than 0.0005 &mgr;m and comparable to the annealed seed layer.