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    Metal-polymer adhesion by low energy bombardment
    2.
    发明授权
    Metal-polymer adhesion by low energy bombardment 失效
    金属 - 聚合物通过低能量轰击粘附

    公开(公告)号：US4886681A

    公开(公告)日：1989-12-12

    申请号：US281960

    申请日：1988-12-06

    申请人： Joachim G. Clabes ,  Peter O. Hahn ,  Paul S. Ho ,  Haralambos Lefakis ,  Gary W. Rubloff

    发明人： Joachim G. Clabes ,  Peter O. Hahn ,  Paul S. Ho ,  Haralambos Lefakis ,  Gary W. Rubloff

    IPC分类号： C23C14/02 ,  C23C14/20 ,  C23C14/22 ,  H05K3/38

    CPC分类号： C23C14/20 ,  C23C14/022 ,  C23C14/22 ,  H05K3/381 ,  H05K3/388

    摘要： A technique is described for improving metal-organic substrate adhesion and for reducing stress between the metal film and the substrate. Low energy reactive ions, electrons, or photons are incident upon the substrate to alter the surface chemistry of the substrate to a depth of from about 10 angstroms to a few hundred angstroms. The energy of the incident reactive ions and electrons is about 50-2000 eV, while the energy of the incident photons is about 0.2-500 eV. Irradiation of the substrate can occur prior to or during metal deposition. For simultaneous metal deposition/particle irradiation, the arrival rates of the metal atoms and the substrate treatment particles are within a few order of magnitude of one another. Room temperatures or elevated temperatures are suitable.

    摘要翻译： 描述了一种用于改善金属 - 有机衬底粘附和减少金属膜和衬底之间的应力的技术。 低能量反应离子，电子或光子入射到衬底上以将衬底的表面化学性质改变到约10埃至几百埃的深度。 入射的反应离子和电子的能量约为50-2000eV，入射光子的能量约为0.2-500eV。 衬底的照射可以在金属沉积之前或期间发生。 为了同时进行金属沉积/颗粒照射，金属原子和基板处理颗粒的到达速率在彼此的几个数量级内。 室温或高温适用。

    Multiple copper vias for integrated circuit metallization
    5.
    发明授权
    Multiple copper vias for integrated circuit metallization 失效
    用于集成电路金属化的多个铜通孔

    公开(公告)号：US07078817B2

    公开(公告)日：2006-07-18

    申请号：US11010596

    申请日：2004-12-13

    申请人： Paul S. Ho ,  Ki-Don Lee ,  Ennis Ogawa ,  Hideki Matsuhashi

    发明人： Paul S. Ho ,  Ki-Don Lee ,  Ennis Ogawa ,  Hideki Matsuhashi

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L22/34 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.

    摘要翻译： 可以减少集成电路的铜基金属化中的电迁移，该集成电路包括通过中间绝缘层将下面的导电线与覆盖的含铜线电连接的第一含铜通孔。 通过形成至少第二含铜通孔，通过与第一含铜通孔平行地电连接下面的导电线路和覆盖的含铜线路穿过中间绝缘层，可以减少电迁移。 多通道可以提供冗余以减少早期故障统计。 此外，由于电流分布在通孔中，所以可以减少电迁移驱动力，并且可以减少在通孔接口处的空隙中的局部焦耳加热。 因此，即使形成通孔，由于焦耳加热，结构也可能不会由于灾难性热失控而失效。

    SELF-ALIGNED MASKS AND METHODS OF USE
    9.
    发明申请
    SELF-ALIGNED MASKS AND METHODS OF USE 有权
    自对准掩模和使用方法

    公开(公告)号：US20150054135A1

    公开(公告)日：2015-02-26

    申请号：US14466059

    申请日：2014-08-22

    申请人： Paul S. Ho ,  Zhuojie Wu

    发明人： Paul S. Ho ,  Zhuojie Wu

    IPC分类号： H01L21/3065 ,  H01L21/308 ,  H01L21/027

    CPC分类号： B81C1/00 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122

    摘要： The disclosure relates to a method for forming a nanoscale structure by forming a pattern on a selectively etched layer located on top of a substrate using lithography, wherein the pattern results a gap having sidewalls, performing RIE on the gap having sidewalls, wherein RIE results in the formation of a self-aligned mask on the bottom wall of the gap with unprotected regions on the bottom wall of the gap near the junctions with the sidewalls, and wet etching the gap having a self-aligned mask and unprotected regions to remove the substrate under the unprotected regions to form a nanoscale structure in the substrate.The disclosure also relates to a nanoscale structure array including a plurality of nanotrenches, nanochannels or nanofins having a width of 50 nm or less and an average variation in width of 5% or less along the entire length of each nanotrench, nanochannel or nanofin.

    摘要翻译： 本公开涉及一种用于通过使用光刻在位于衬底顶部的选择性蚀刻层上形成图案形成纳米尺度结构的方法，其中所述图案形成具有侧壁的间隙，在具有侧壁的间隙上执行RIE，其中RIE导致 在与侧壁接合的间隙的底壁上的未保护区域的间隙的底壁上形成自对准掩模，并且湿蚀刻具有自对准掩模和未保护区域的间隙以去除衬底 在未保护的区域下，在衬底中形成纳米尺度结构。 本公开还涉及纳米尺度结构阵列，其包括沿着每个纳米管，纳米通道或纳米芬的整个长度的宽度为50nm或更小的宽度为5％或更小的多个纳米管，纳米通道或纳米线。

    Multiple copper vias for integrated circuit metallization and methods of fabricating same
    10.
    发明授权
    Multiple copper vias for integrated circuit metallization and methods of fabricating same 失效
    用于集成电路金属化的多个铜通孔及其制造方法

    公开(公告)号：US06919639B2

    公开(公告)日：2005-07-19

    申请号：US10271284

    申请日：2002-10-15

    申请人： Paul S. Ho ,  Ki-Don Lee ,  Ennis Ogawa ,  Hideki Matsuhashi

    发明人： Paul S. Ho ,  Ki-Don Lee ,  Ennis Ogawa ,  Hideki Matsuhashi

    IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/544 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L22/34 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.

    摘要翻译： 可以减少集成电路的铜基金属化中的电迁移，该集成电路包括通过中间绝缘层将下面的导电线与覆盖的含铜线电连接的第一含铜通孔。 通过形成至少第二含铜通孔，通过与第一含铜通孔平行地电连接下面的导电线路和覆盖的含铜线路穿过中间绝缘层，可以减少电迁移。 多通道可以提供冗余以减少早期故障统计。 此外，由于电流分布在通孔中，所以可以减少电迁移驱动力，并且可以减少在通孔接口处的空隙中的局部焦耳加热。 因此，即使形成通孔，由于焦耳加热，结构也可能不会由于灾难性热失控而失效。