公开(公告)号：US20200243449A1

公开(公告)日：2020-07-30

申请号：US16261566

申请日：2019-01-30

申请人： Powertech Technology Inc.

发明人： Chia-Wei Chiang ,  Li-Chih Fang ,  Wen-Jeng Fan

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

摘要： A package structure includes a redistribution structure, a bridge die, a plurality of conductive pillars, at least two dies, and an insulating encapsulant. The bridge die provides an electrical connection between the at least two dies. The conductive pillars provide an electrical connection between the at least two dies and the redistribution structure. The insulating encapsulant is disposed on the redistribution structure, encapsulates the bridge die and the conductive pillars, and covers each of the at least two dies. The bridge die of the package structure may be used to route signals between the at least two dies, allowing for a higher density of interconnecting routes between the at least two dies.

公开(公告)号：US10431549B2

公开(公告)日：2019-10-01

申请号：US15867670

申请日：2018-01-10

申请人： Powertech Technology Inc.

发明人： Chien-Wen Huang ,  Chia-Wei Chiang ,  Wen-Jeng Fan ,  Li-Chih Fang

IPC分类号： H01L23/495 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L25/10

摘要： A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.

公开(公告)号：US20170309597A1

公开(公告)日：2017-10-26

申请号：US15491982

申请日：2017-04-20

申请人： Powertech Technology Inc.

发明人： Yong-Cheng Chuang ,  Kuo-Ting Lin ,  Li-Chih Fang ,  Chia-Jen Chou

IPC分类号： H01L25/065 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0237 ,  H01L2224/02373 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

摘要： A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is encapsulated using a first encapsulant. The first encapsulant exposes part of the first die. A redistribution layer (RDL) is formed over the first encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first surface faces the first encapsulant. The first encapsulant and the first die are separated from the carrier. A plurality of second dies are disposed on the second surface of the RDL. The second dies are encapsulated using the second encapsulant. A plurality of conductive terminals are formed on the first surface of the RDL.

公开(公告)号：US20170256471A1

公开(公告)日：2017-09-07

申请号：US15432932

申请日：2017-02-15

申请人： POWERTECH TECHNOLOGY INC.

发明人： Li-Chih Fang ,  Chia-Chang Chang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang ,  Kee-Wei Chung ,  Chia-Wen Lien

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L27/146 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498

CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13027 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/0132 ,  H01L2924/15311

摘要： A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.

公开(公告)号：US10276510B2

公开(公告)日：2019-04-30

申请号：US15713717

申请日：2017-09-25

申请人： Powertech Technology Inc.

发明人： Chia-Wei Chiang ,  Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin

IPC分类号： H01L21/56 ,  H01L23/552 ,  H01L23/00

摘要： A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.

公开(公告)号：US09831219B2

公开(公告)日：2017-11-28

申请号：US15491982

申请日：2017-04-20

申请人： Powertech Technology Inc.

发明人： Yong-Cheng Chuang ,  Kuo-Ting Lin ,  Li-Chih Fang ,  Chia-Jen Chou

IPC分类号： H01L21/56 ,  H01L25/18 ,  H01L21/78 ,  H01L23/28 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0237 ,  H01L2224/02373 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

摘要： A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is encapsulated using a first encapsulant. The first encapsulant exposes part of the first die. A redistribution layer (RDL) is formed over the first encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first surface faces the first encapsulant. The first encapsulant and the first die are separated from the carrier. A plurality of second dies are disposed on the second surface of the RDL. The second dies are encapsulated using the second encapsulant. A plurality of conductive terminals are formed on the first surface of the RDL.

公开(公告)号：US09761568B2

公开(公告)日：2017-09-12

申请号：US15383560

申请日：2016-12-19

申请人： POWERTECH TECHNOLOGY INC.

发明人： Li-Chih Fang ,  Chia-Wei Chang ,  Kuo-Ting Lin ,  Yong-Cheng Chuang

IPC分类号： H01L25/11 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/304

CPC分类号： H01L25/117 ,  H01L21/304 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3171 ,  H01L24/09 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/69 ,  H01L24/70 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/18162 ,  H01L2224/83005

摘要： A fan out type multi-chip stacked package includes a chip stacked assembly having a plurality of chips vertically stacked. The electrodes of the chips and one active surface among all active surfaces are not covered by the stacked chips. A plurality of flip-chip bumps of a dummy flip chip are coupled to the electrodes of the chips. An encapsulant encapsulates the chip stacked assembly and the flip-chip bumps. The encapsulant has a planar surface. The flip-chip bumps have a plurality of bonding surfaces exposed from and coplanar to the planar surface. A redistribution layer is disposed on the planar surface and includes a plurality of fan out circuits electrically connected the bonding surfaces of the flip-chip bumps. Thus, the package has better resistance against mold flow impact to effectively reduce the risk of wire sweeping.

公开(公告)号：US20190214367A1

公开(公告)日：2019-07-11

申请号：US15867613

申请日：2018-01-10

申请人： Powertech Technology Inc.

发明人： Ming-Chih Chen ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Chi-An Wang ,  Hsien-Wen Hsu ,  Li-Chih Fang

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/28 ,  H01L23/538 ,  H01L23/552

CPC分类号： H01L25/0657 ,  H01L23/28 ,  H01L23/5384 ,  H01L23/552 ,  H01L25/50

摘要： A stacked package has plurality of chip packages stacked on a base. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on a lateral side of the chip package. The lateral trace is formed through the encapsulant and electrically connects to the cut edges of the chip packages. The base has an interconnect structure to form the electrical connection between the lateral trace and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.

公开(公告)号：US20190096821A1

公开(公告)日：2019-03-28

申请号：US15713717

申请日：2017-09-25

申请人： Powertech Technology Inc.

发明人： Chia-Wei Chiang ,  Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin

IPC分类号： H01L23/552 ,  H01L23/00 ,  H01L21/56

摘要： A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.

公开(公告)号：US09972554B2

公开(公告)日：2018-05-15

申请号：US15432932

申请日：2017-02-15

申请人： POWERTECH TECHNOLOGY INC.

发明人： Li-Chih Fang ,  Chia-Chang Chang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang ,  Kee-Wei Chung ,  Chia-Wen Lien

IPC分类号： H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L27/146

CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13027 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/0132 ,  H01L2924/15311

摘要： A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.