公开(公告)号：US09466554B2

公开(公告)日：2016-10-11

申请号：US14274517

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L21/4763 ,  H01L23/48 ,  H01L23/50 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

Abstract translation: 一些新颖的特征涉及包括封装层，穿过封装层的通孔结构和衬垫的集成器件。 通孔结构包括通孔，其包括第一侧，第二侧和第三侧。 通孔结构还包括至少围绕通孔的第一侧和第三侧的阻挡层。 焊盘直接耦合到通孔结构的阻挡层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的第一介电层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的衬底。 在一些实施方案中，集成器件包括耦合到衬底的第一管芯，其中封装层封装第一管芯。 在一些实施方式中，通孔包括被配置为作为垫进行操作的部分。

公开(公告)号：US09401350B1

公开(公告)日：2016-07-26

申请号：US14812476

申请日：2015-07-29

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Jae Sik Lee ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L25/18 ,  H01L23/522 ,  H01L23/532 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H01L21/52 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31

CPC classification number: H01L21/52 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A package-on-package (POP) structure is disclosed. The POP structure includes a first die, a second die, and a photo-imaged dielectric (PID) layer. The PID layer is disposed between the first die and the second die. The POP structure also includes a first conductive path from the first die through the PID layer to the second die. The first conductive path extends directly through a first area of the PID layer directly between the first die and the second die. The POP structure further includes a second conductive path from the first die through the PID layer to the second die. A particular portion of the second conductive path is perpendicular to the first conductive path and extends through a second area of the PID layer not directly between the first die and the second die.

Abstract translation: 公开了一种封装封装（POP）结构。 POP结构包括第一裸片，第二裸片和光成像电介质（PID）层。 PID层设置在第一管芯和第二管芯之间。 POP结构还包括从第一管芯通过PID层到第二管芯的第一导电路径。 第一导电路径直接在第一管芯和第二管芯之间直接延伸通过PID层的第一区域。 POP结构还包括从第一管芯通过PID层到第二管芯的第二导电路径。 第二导电路径的特定部分垂直于第一导电路径并且不直接在第一管芯和第二管芯之间延伸穿过PID层的第二区域。

公开(公告)号：US20160133571A1

公开(公告)日：2016-05-12

申请号：US14535966

申请日：2014-11-07

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.

Abstract translation: 一些新颖的特征涉及包括封装部分和再分配部分的集成器件封装。 封装部分包括第一管芯，耦合到第一管芯的第一组通孔，第二管芯，耦合到第二管芯的第二组通孔，桥接器和封装层。 桥被配置为在第一管芯和第二管芯之间提供电路径。 桥通过第一组通孔耦合到第一个模具。 桥通过第二组通孔进一步耦合到第二管芯。 封装层至少部分地封装第一管芯，第二管芯，桥接器，第一组通孔和第二组通孔。 再分配部分耦合到封装部分。 再分配部分包括一组再分布互连和至少一个电介质层。

公开(公告)号：US09230936B2

公开(公告)日：2016-01-05

申请号：US14196817

申请日：2014-03-04

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Hong Bok We ,  Jae Sik Lee ,  Shiqun Gu

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24137 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1815 ,  H01L2924/014

Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die coupled to a first surface of the base portion, and an underfill between the first die and the base portion. The base portion includes a dielectric layer, and a set of redistribution metal layers. In some implementations, the integrated device further includes an encapsulation material that encapsulates the first die. In some implementations, the integrated device further includes a second die coupled to the first surface of the base portion. In some implementations, the integrated device further includes a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars.

Abstract translation: 一些新颖的特征涉及一种集成器件（例如，集成封装），其包括用于集成器件的基座部分，耦合到基部部分的第一表面的第一管芯以及第一管芯和基部之间的底部填充。 基部包括电介质层和一组再分布金属层。 在一些实施方案中，集成器件还包括封装第一裸片的封装材料。 在一些实施方案中，集成装置还包括耦合到基部的第一表面的第二模具。 在一些实施方案中，集成器件还包括在基部上的一组互连，该组互连电耦合第一管芯和第二管芯。 在一些实施方案中，第一管芯包括第一组互连柱，并且第二管芯包括第二组互连柱。

公开(公告)号：US20140252561A1

公开(公告)日：2014-09-11

申请号：US13791223

申请日：2013-03-08

Applicant: QUALCOMM INCORPORATED

Inventor： Durodami Joscelyn Lisk ,  Vidhya Ramachandran ,  Jae Sik Lee

IPC: H01L23/538 ,  H01L25/00

Abstract: A via-enabled package-on-package circuit includes a first package including a first package die having a plurality of through substrate vias (TSVs). The TSVs are configured to carry the input/output signaling for at least one second package die.

Abstract translation: 通孔使能封装电路包括包括具有多个贯穿衬底通孔（TSV）的第一封装管芯的第一封装。 TSV被配置为承载用于至少一个第二封装管芯的输入/输出信号。

公开(公告)号：US09613942B2

公开(公告)日：2017-04-04

申请号：US14733201

申请日：2015-06-08

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Kyu-Pyung Hwang ,  Hong Bok We

IPC: H01L25/18 ,  H01L23/498 ,  H01L25/065 ,  H01L23/50 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/14 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L25/18 ,  H01L21/486 ,  H01L21/565 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/00 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/92225 ,  H01L2225/06548 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

公开(公告)号：US20160225748A1

公开(公告)日：2016-08-04

申请号：US14609079

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Jae Sik Lee ,  Kyu-Pyung Hwang

IPC: H01L25/10 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L23/49811 ,  H01L23/5389 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157

Abstract: A method for forming a package-on-package (POP) structure is disclosed. The method includes placing a post on a first integrated circuit (IC) package such that a solder coating disposed on a first surface of the post is between the post and a second surface of the first IC package. The post is placed at a distance from a die along a particular axis of the die. The particular axis is substantially parallel to the second surface. The first IC package includes the die. The method also includes forming a conductive path between a second IC package and the first IC package via the post and a solder bump. The solder bump is disposed between the post and the second IC package.

Abstract translation: 公开了一种用于形成封装封装（POP）结构的方法。 该方法包括将柱放置在第一集成电路（IC）封装上，使得布置在柱的第一表面上的焊料涂层位于第一IC封装的柱和第二表面之间。 柱沿模具的特定轴线放置在离模具一定距离处。 特定轴线基本上平行于第二表面。 第一个IC封装包括裸片。 该方法还包括在第二IC封装和第一IC封装之间经由柱和焊料凸块形成导电路径。 焊料凸块设置在柱和第二IC封装之间。

公开(公告)号：US20160141234A1

公开(公告)日：2016-05-19

申请号：US14543560

申请日：2014-11-17

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L23/498

CPC classification number: H01L23/5385 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/3436 ,  H05K3/4694 ,  H05K2203/061 ,  H01L2924/00

Abstract: An integrated device package includes a base portion, a redistribution portion, a first die and a second die. The base portion includes a photo imageable layer, a bridge that is at least partially embedded in the photo imageable layer, and a set of vias in the photo imageable layer. The bridge includes a first set of interconnects comprising a first density. The set of vias includes a second density. The redistribution portion is coupled to base portion. The redistribution portion includes at least one dielectric layer, a second set of interconnects coupled to the first set of interconnects, and a third set of interconnects coupled to the set of vias. The first die is coupled to the redistribution portion. The second die is coupled to the redistribution portion, where the first die and the second die are coupled to each other through an electrical path that includes the bridge.

Abstract translation: 集成器件封装包括基部，再分配部分，第一管芯和第二管芯。 基部包括可照像图像层，至少部分地嵌入在可照光成像层中的桥以及可照片成像层中的一组通孔。 桥包括包括第一密度的第一组互连。 该组通孔包括第二密度。 再分配部分耦合到基部。 再分配部分包括耦合到第一组互连的至少一个电介质层，第二组互连以及耦合到该组通孔的第三组互连。 第一管芯耦合到再分配部分。 第二管芯耦合到再分配部分，其中第一管芯和第二管芯通过包括桥的电路相互连接。

公开(公告)号：US20150228556A1

公开(公告)日：2015-08-13

申请号：US14274517

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/50

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

Abstract translation: 一些新颖的特征涉及包括封装层，穿过封装层的通孔结构和焊盘的集成器件。 通孔结构包括通孔，其包括第一侧，第二侧和第三侧。 通孔结构还包括至少围绕通孔的第一侧和第三侧的阻挡层。 焊盘直接耦合到通孔结构的阻挡层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的第一介电层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的衬底。 在一些实施方案中，集成器件包括耦合到衬底的第一管芯，其中封装层封装第一管芯。 在一些实施方式中，通孔包括被配置为作为垫进行操作的部分。

公开(公告)号：US20170243845A1

公开(公告)日：2017-08-24

申请号：US15048906

申请日：2016-02-19

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L21/3105

CPC classification number: H01L24/14 ,  H01L21/31051 ,  H01L21/31058 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3511

Abstract: A fan-out wafer-level-process integrated circuit is provided in which a plurality of interconnects couple to pads on an encapsulated die. The interconnects have a pad-facing surface that couples to a corresponding pad through a seed layer. The seed layer does not cover the sidewalls of the interconnects.