公开(公告)号：US08362571B1

公开(公告)日：2013-01-29

申请号：US13016660

申请日：2011-01-28

申请人： Qingguo Wu ,  James S. Sims ,  Mandyam Sriram ,  Seshasayee Varadarajan ,  Haiying Fu ,  Pramod Subramonium ,  Jon Henri ,  Sirish Reddy

发明人： Qingguo Wu ,  James S. Sims ,  Mandyam Sriram ,  Seshasayee Varadarajan ,  Haiying Fu ,  Pramod Subramonium ,  Jon Henri ,  Sirish Reddy

IPC分类号： H01L21/02

CPC分类号： H01L21/02115 ,  H01L21/02274 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7848

摘要： Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide amorphous carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.

摘要翻译： 晶体管架构和制造工艺产生通道应变，而不会不利地影响晶体管制造工艺的效率，同时保持材料质量并增强所得晶体管的性能。 产生晶体管应变是使用在至少源极和漏极区上作为覆盖层施加的高度压缩的后自适应硅化物非晶碳覆盖层的PMOS器件。 来自该覆盖层的应力通过源极 - 漏极区域单轴转移到PMOS沟道，以在PMOS沟道中产生压缩应变。

公开(公告)号：US07906817B1

公开(公告)日：2011-03-15

申请号：US12134969

申请日：2008-06-06

申请人： Qingguo Wu ,  James S. Sims ,  Mandyam Sriram ,  Seshasayee Varadarajan ,  Haiying Fu ,  Pramod Subramonium ,  Jon Henri ,  Sirish Reddy

发明人： Qingguo Wu ,  James S. Sims ,  Mandyam Sriram ,  Seshasayee Varadarajan ,  Haiying Fu ,  Pramod Subramonium ,  Jon Henri ,  Sirish Reddy

IPC分类号： H01L29/76

CPC分类号： H01L21/02115 ,  H01L21/02274 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7848

摘要： Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide amorphous carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.

摘要翻译： 晶体管架构和制造工艺产生通道应变，而不会不利地影响晶体管制造工艺的效率，同时保持材料质量并增强所得晶体管的性能。 产生晶体管应变是使用在至少源极和漏极区上作为覆盖层施加的高度压缩的后自适应硅化物非晶碳覆盖层的PMOS器件。 来自该覆盖层的应力通过源极 - 漏极区域单轴转移到PMOS沟道，以在PMOS沟道中产生压缩应变。

公开(公告)号：US07998881B1

公开(公告)日：2011-08-16

申请号：US12134961

申请日：2008-06-06

申请人： Qingguo Wu ,  James S. Sims ,  Mandyam Sriram ,  Seshasayee Varadarajan ,  Akhil Singhal

发明人： Qingguo Wu ,  James S. Sims ,  Mandyam Sriram ,  Seshasayee Varadarajan ,  Akhil Singhal

IPC分类号： H01L21/469

CPC分类号： H01L21/76834 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/7843

摘要： Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide boron doped carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.

摘要翻译： 晶体管架构和制造工艺产生通道应变，而不会不利地影响晶体管制造工艺的效率，同时保持材料质量并增强所得晶体管的性能。 产生晶体管应变是使用在至少源极和漏极区上作为覆盖层施加的高度压缩的后硅化物硼掺杂碳覆盖层的PMOS器件。 来自该覆盖层的应力通过源极 - 漏极区域单轴转移到PMOS沟道，以在PMOS沟道中产生压缩应变。

公开(公告)号：US07799671B1

公开(公告)日：2010-09-21

申请号：US12630457

申请日：2009-12-03

申请人： Ananda Banerji ,  George Andrew Antonelli ,  Jennifer O'Ioughlin ,  Mandyam Sriram ,  Bart van Schravendijk ,  Seshasayee Varadarajan

发明人： Ananda Banerji ,  George Andrew Antonelli ,  Jennifer O'Ioughlin ,  Mandyam Sriram ,  Bart van Schravendijk ,  Seshasayee Varadarajan

IPC分类号： H01L21/44

CPC分类号： H01L21/02074 ,  C23C16/0227 ,  C23C16/0272 ,  C23C16/36 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a source layer of dopant-generating material (e.g., material generating B, Al, Ti, etc.) over an exposed copper line, converting the upper portion of the source layer to a passivated layer (e.g., nitride or oxide) while allowing an unmodified portion of a dopant-generating source layer to remain in contact with copper, and, subsequently, allowing the dopant from the unmodified portion of source layer to controllably diffuse into and/or react with copper, thereby forming a thin protective cap within copper line. The cap may contain a solid solution or an alloy of copper with the dopant.

摘要翻译： 使用驻留在金属线和电介质扩散阻挡层（或蚀刻停止）层之间的界面处的保护盖来改善互连的电迁移性能。 通过在暴露的铜线上沉积产生掺杂剂的材料的源层（例如，产生B，Al，Ti等的材料）形成保护盖，将源极的上部转化为钝化层（例如，氮化物 或氧化物），同时允许掺杂剂发生源层的未修饰部分与铜保持接触，并且随后允许来自源层的未修饰部分的掺杂剂可控地扩散到铜中和/或与铜反应，从而形成 铜线内薄保护帽。 盖可以包含铜与掺杂剂的固溶体或合金。

公开(公告)号：US07648899B1

公开(公告)日：2010-01-19

申请号：US12074108

申请日：2008-02-28

申请人： Ananda Banerji ,  George Andrew Antonelli ,  Jennifer O'loughlin ,  Mandyam Sriram ,  Bart Van Schravendijk ,  Seshasayee Varadarajan

发明人： Ananda Banerji ,  George Andrew Antonelli ,  Jennifer O'loughlin ,  Mandyam Sriram ,  Bart Van Schravendijk ,  Seshasayee Varadarajan

IPC分类号： H01L21/44 ,  H01L21/31

CPC分类号： H01L21/02074 ,  C23C16/0227 ,  C23C16/0272 ,  C23C16/36 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a source layer of dopant-generating material (e.g., material generating B, Al, Ti, etc.) over an exposed copper line, converting the upper portion of the source layer to a passivated layer (e.g., nitride or oxide) while allowing an unmodified portion of a dopant-generating source layer to remain in contact with copper, and, subsequently, allowing the dopant from the unmodified portion of source layer to controllably diffuse into and/or react with copper, thereby forming a thin protective cap within copper line. The cap may contain a solid solution or an alloy of copper with the dopant.

公开(公告)号：US20100317198A1

公开(公告)日：2010-12-16

申请号：US12533960

申请日：2009-07-31

申请人： George Andrew Antonelli ,  Jennifer O' Loughlin ,  Tony Xavier ,  Mandyam Sriram ,  Bart van Schravendijk ,  Vishwanathan Rangarajan ,  Seshasayee Varadarajan ,  Bryan L. Buckalew

发明人： George Andrew Antonelli ,  Jennifer O' Loughlin ,  Tony Xavier ,  Mandyam Sriram ,  Bart van Schravendijk ,  Vishwanathan Rangarajan ,  Seshasayee Varadarajan ,  Bryan L. Buckalew

IPC分类号： H01L21/465 ,  C23C16/50

CPC分类号： H01L21/02074 ,  C23C16/0245 ,  C23C16/54 ,  H01L21/0206 ,  H01L21/28185 ,  H01L21/3105 ,  H01L21/67201 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76886 ,  H01L28/60

摘要： Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, and a remote plasma source configured to provide a remote plasma to the load lock.

摘要翻译： 本文公开了通过远程等离子体处理在半导体晶片制造工艺中清洁界面的实施例。 例如，在一个所公开的实施例中，半导体处理装置包括处理室，经由传送端口耦合到处理室的负载锁定，设置在负载锁中并被配置为支撑加载锁中的晶片的晶片基座，以及 远程等离子体源，被配置为向负载锁提供远程等离子体。

公开(公告)号：US20110120377A1

公开(公告)日：2011-05-26

申请号：US13019854

申请日：2011-02-02

申请人： George Andrew Antonelli ,  Jennifer O'Loughlin ,  Tony Xavier ,  Mandyam Sriram ,  Bart Van Schravendijk ,  Vishwanathan Rangarajan ,  Seshasayee Varadarajan ,  Bryan L. Buckalew

发明人： George Andrew Antonelli ,  Jennifer O'Loughlin ,  Tony Xavier ,  Mandyam Sriram ,  Bart Van Schravendijk ,  Vishwanathan Rangarajan ,  Seshasayee Varadarajan ,  Bryan L. Buckalew

IPC分类号： H01L21/4763

CPC分类号： H01L21/02068 ,  C23C16/0245 ,  C23C16/54 ,  C23C16/56 ,  H01L21/0206 ,  H01L21/02074 ,  H01L21/02315 ,  H01L21/3105 ,  H01L21/67201 ,  H01L21/76826 ,  H01L21/76862 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.

摘要翻译： 本文公开了通过远程等离子体处理在半导体晶片制造工艺中清洁界面的实施例。 例如，在一个所公开的实施例中，半导体处理装置包括处理室，经由传送端口耦合到处理室的负载锁，设置在负载锁中并被配置为支撑加载锁中的晶片的晶片基座， 远程等离子体源，被配置为将远程等离子体提供给负载锁定;以及离子过滤器，其布置在远程等离子体源和晶片基座之间。

公开(公告)号：US07858510B1

公开(公告)日：2010-12-28

申请号：US12689803

申请日：2010-01-19

申请人： Ananda Banerji ,  George Andrew Antonelli ,  Jennifer O'loughlin ,  Mandyam Sriram ,  Bart van Schravendijk ,  Seshasayee Varadarajan

发明人： Ananda Banerji ,  George Andrew Antonelli ,  Jennifer O'loughlin ,  Mandyam Sriram ,  Bart van Schravendijk ,  Seshasayee Varadarajan

IPC分类号： H01L21/44 ,  B05D5/12

CPC分类号： C23C16/0227 ,  C23C16/0272 ,  C23C16/36 ,  H01L21/02074 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a first layer of aluminum-containing material over an exposed copper line by treating an oxide-free copper surface with an organoaluminum compound in an absence of plasma at a substrate temperature of at least about 350° C. The formed aluminum-containing layer is passivated either partially or completely in a chemical conversion which forms Al—N, Al—O or both Al—O and Al—N bonds in the layer. Passivation is performed in some embodiments by contacting the substrate having an exposed first layer with an oxygen-containing reactant and/or nitrogen-containing reactant in the absence of plasma. Protective caps can be formed on substrates comprising exposed ULK dielectric. The aluminum-containing layer residing on the dielectric portion will typically spontaneously form non-conductive layer comprising Al—O bonds.

摘要翻译： 使用驻留在金属线和电介质扩散阻挡层（或蚀刻停止）层之间的界面处的保护盖来改善互连的电迁移性能。 通过在不存在等离子体的条件下，在至少约350℃的衬底温度下，通过用有机铝化合物处理无氧化物的铜表面，在暴露的铜线上沉积第一层含铝材料形成保护帽。形成 含铝层在化学转化中被部分或完全钝化，该化学转化在层中形成Al-N，Al-O或Al-O和Al-N键。 在一些实施方案中，通过在不存在等离子体的情况下将具有暴露的第一层的衬底与含氧反应物和/或含氮反应物接触来进行钝化。 可以在包括暴露的ULK电介质的基板上形成保护盖。 驻留在电介质部分上的含铝层通常会自发形成包含Al-O键的非导电层。

公开(公告)号：US20100317178A1

公开(公告)日：2010-12-16

申请号：US12484047

申请日：2009-06-12

申请人： George Andrew Antonelli ,  Jennifer O' Loughlin ,  Tony Xavier ,  Mandyam Sriram ,  Bart Van Schravendijk ,  Vishwanathan Rangarajan ,  Seshasayee Varadarajan ,  Bryan L. Buckalew

发明人： George Andrew Antonelli ,  Jennifer O' Loughlin ,  Tony Xavier ,  Mandyam Sriram ,  Bart Van Schravendijk ,  Vishwanathan Rangarajan ,  Seshasayee Varadarajan ,  Bryan L. Buckalew

IPC分类号： H01L21/3205 ,  C23C16/513 ,  C23C16/02 ,  H01L21/31

CPC分类号： H01L21/02068 ,  C23C16/0245 ,  C23C16/54 ,  C23C16/56 ,  H01L21/0206 ,  H01L21/02074 ,  H01L21/02315 ,  H01L21/3105 ,  H01L21/67201 ,  H01L21/76826 ,  H01L21/76862 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.

摘要翻译： 本文公开了通过远程等离子体处理在半导体晶片制造工艺中清洁界面的实施例。 例如，在一个所公开的实施例中，半导体处理装置包括处理室，经由传送端口耦合到处理室的负载锁，设置在负载锁中并被配置为支撑加载锁中的晶片的晶片基座， 远程等离子体源，被配置为将远程等离子体提供给负载锁定;以及离子过滤器，其布置在远程等离子体源和晶片基座之间。

公开(公告)号：US08217513B2

公开(公告)日：2012-07-10

申请号：US13019854

申请日：2011-02-02

申请人： George Andrew Antonelli ,  Jennifer O'Loughlin ,  Tony Xavier ,  Mandyam Sriram ,  Bart van Schravendijk ,  Vishwanathan Rangarajan ,  Seshasayee Varadarajan ,  Bryan L. Buckalew

发明人： George Andrew Antonelli ,  Jennifer O'Loughlin ,  Tony Xavier ,  Mandyam Sriram ,  Bart van Schravendijk ,  Vishwanathan Rangarajan ,  Seshasayee Varadarajan ,  Bryan L. Buckalew

IPC分类号： H01L23/34

CPC分类号： H01L21/02068 ,  C23C16/0245 ,  C23C16/54 ,  C23C16/56 ,  H01L21/0206 ,  H01L21/02074 ,  H01L21/02315 ,  H01L21/3105 ,  H01L21/67201 ,  H01L21/76826 ,  H01L21/76862 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus includes a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.

摘要翻译： 本文公开了通过远程等离子体处理在半导体晶片制造工艺中清洁界面的实施例。 例如，在一个所公开的实施例中，半导体处理装置包括处理室，经由传送端口与处理室耦合的负载锁定，设置在负载锁中并被配置为支撑加载锁中的晶片的晶片基座， 远程等离子体源，被配置为将远程等离子体提供给负载锁定;以及离子过滤器，其布置在远程等离子体源和晶片基座之间。