公开(公告)号：US20160365316A1

公开(公告)日：2016-12-15

申请号：US15247128

申请日：2016-08-25

Applicant: Renesas Electronics Corporation

Inventor： Yuichi MIYAGAWA ,  Hideki FUJII ,  Kenji FURUYA

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/552 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/07 ,  H01L23/498 ,  H01L23/433

CPC classification number: H01L23/5227 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/12 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/4334 ,  H01L23/48 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/50 ,  H01L23/552 ,  H01L23/564 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L28/10 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Abstract translation: 半导体芯片安装在互连基板的第一表面上，并且具有多层互连层。 第一电感器形成在多层互连层上，其布线轴线方向指向互连基板。 第二电感器形成在多层互连层上，其布线轴线方向指向互连基板。 第二电感器与第一电感器相反。 密封树脂至少密封互连基板的第一表面和半导体芯片。 在位于多层互连层和密封树脂的边界表面的至少第一电感器和第二电感器之间的部分的整个区域上形成凹槽。

公开(公告)号：US20130127050A1

公开(公告)日：2013-05-23

申请号：US13737494

申请日：2013-01-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuichi MIYAGAWA ,  Takehiko Maeda

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29034 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the first semiconductor chip being mounted on the main surface of the substrate, a plurality of bumps provided between the main surface of the substrate and the lower surface of the first semiconductor chip, a second semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the second semiconductor chip being mounted on the upper surface of the first semiconductor chip such that the side surface of the second semiconductor chip is positioned outward from the side surface of the first semiconductor chip.

Abstract translation: 半导体器件包括具有主表面和与主表面相对的后表面的衬底，第一半导体芯片，其具有上表面和与第一表面相对的下表面，侧表面设置在其间，第一半导体芯片被安装 在基板的主表面上，设置在基板的主表面和第一半导体芯片的下表面之间的多个凸块，具有与第一表面相对的上表面和下表面的第二半导体芯片， 表面，第二半导体芯片安装在第一半导体芯片的上表面上，使得第二半导体芯片的侧表面位于第一半导体芯片的侧表面的外侧。

公开(公告)号：US20140346636A1

公开(公告)日：2014-11-27

申请号：US14458709

申请日：2014-08-13

Applicant: Renesas Electronics Corporation

Inventor： Yuichi MIYAGAWA ,  Hideki FUJII ,  Kenji FURUYA

IPC: H01L49/02 ,  H01L23/12 ,  H01L23/28

CPC classification number: H01L23/5227 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/12 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/4334 ,  H01L23/48 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/50 ,  H01L23/552 ,  H01L23/564 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L28/10 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Abstract translation: 半导体芯片安装在互连基板的第一表面上，并且具有多层互连层。 第一电感器形成在多层互连层上，其布线轴线方向指向互连基板。 第二电感器形成在多层互连层上，其布线轴线方向指向互连基板。 第二电感器与第一电感器相反。 密封树脂至少密封互连基板的第一表面和半导体芯片。 在位于多层互连层和密封树脂的边界表面的至少第一电感器和第二电感器之间的部分的整个区域上形成凹槽。