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    High speed VLSI digital tester architecture for real-time output timing acquisition, results accumulation, and analysis
    2.
    发明授权
    High speed VLSI digital tester architecture for real-time output timing acquisition, results accumulation, and analysis 有权
    高速VLSI数字测试仪架构，用于实时输出定时采集，结果积累和分析

    公开(公告)号：US06768297B2

    公开(公告)日：2004-07-27

    申请号：US09725401

    申请日：2000-11-29

    申请人： John C. Johnson ,  Christopher J. Nelson ,  Donald E. Edenfeld

    发明人： John C. Johnson ,  Christopher J. Nelson ,  Donald E. Edenfeld

    IPC分类号： G01R3128

    CPC分类号： G01R31/31937

    摘要： A tester for testing a digital device. The tester includes a plurality of time measurement units to measure transition timing values of output data of each output pin of the digital device in each test cycle. A plurality of result operations units performs real-time arithmetic operations on the measured transition timing values to produce a pass/fail result and additional test results. A plurality of result accumulators stores the pass/fail result and a number of selected test results. And a capture/analysis engine captures and analyzes the pass/fail result and the selected results to provide comprehensive test performance of the digital device.

    摘要翻译： 用于测试数字设备的测试仪。 测试仪包括多个时间测量单元，用于测量每个测试周期中数字设备的每个输出引脚的输出数据的转换定时值。 多个结果操作单元对所测量的过渡时间值执行实时算术运算，以产生通过/失败结果和附加测试结果。 多个结果累加器存储通过/失败结果以及所选择的测试结果的数量。 捕获/分析引擎捕获并分析通过/失败结果和选定的结果，以提供数字设备的综合测试性能。

    INPUT/OUTPUT DELAY TESTING FOR DEVICES UTILIZING ON-CHIP DELAY GENERATION
    3.
    发明申请
    INPUT/OUTPUT DELAY TESTING FOR DEVICES UTILIZING ON-CHIP DELAY GENERATION 有权
    使用片上延迟生成的设备的输入/输出延迟测试

    公开(公告)号：US20140189457A1

    公开(公告)日：2014-07-03

    申请号：US13728741

    申请日：2012-12-27

    申请人： Tak M. Mak ,  Christopher J. Nelson ,  David J. Zimmerman ,  Derek B. Feltham

    发明人： Tak M. Mak ,  Christopher J. Nelson ,  David J. Zimmerman ,  Derek B. Feltham

    IPC分类号： G01R31/3177

    CPC分类号： G01R31/31716 ,  G01R31/3016

    摘要： I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.

    摘要翻译： 利用片上延迟生成的器件进行I / O延迟测试。 装置的实施例包括I / O缓冲电路，缓冲电路中的至少一个包括被耦合用于缓冲电路的环回测试的发射机和接收机; 以及用于所述至少一个缓冲电路的环回测试的测试电路，所述环回测试包括确定由所述缓冲器电路的发射机发送的测试数据是否与由所述相应耦合的接收机接收的测试数据相匹配。 测试电路包括延迟线，用于从用于测试至少一个缓冲电路的发射时钟信号提供延迟值，提供计数以选择多个延迟值中的一个的计数器， 回测试。

    Input/output delay testing for devices utilizing on-chip delay generation
    4.
    发明授权
    Input/output delay testing for devices utilizing on-chip delay generation 有权
    使用片上延迟生成的器件的输入/输出延迟测试

    公开(公告)号：US09110134B2

    公开(公告)日：2015-08-18

    申请号：US13728741

    申请日：2012-12-27

    申请人： Tak M. Mak ,  Christopher J. Nelson ,  David J. Zimmerman ,  Derek B. Feltham

    发明人： Tak M. Mak ,  Christopher J. Nelson ,  David J. Zimmerman ,  Derek B. Feltham

    IPC分类号： G01R31/30 ,  G01R31/317

    CPC分类号： G01R31/31716 ,  G01R31/3016

    摘要： I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.

    摘要翻译： 利用片上延迟生成的器件进行I / O延迟测试。 装置的实施例包括I / O缓冲电路，缓冲电路中的至少一个包括被耦合用于缓冲电路的环回测试的发射机和接收机; 以及用于所述至少一个缓冲电路的环回测试的测试电路，所述环回测试包括确定由所述缓冲器电路的发射机发送的测试数据是否与由所述相应耦合的接收机接收的测试数据相匹配。 测试电路包括延迟线，用于从用于测试至少一个缓冲电路的发射时钟信号提供延迟值，提供计数以选择多个延迟值中的一个的计数器， 回测试。

    System and method for multi-protocol radio-frequency identification
    5.
    发明授权
    System and method for multi-protocol radio-frequency identification 有权

    公开(公告)号：US08411764B2

    公开(公告)日：2013-04-02

    申请号：US11893679

    申请日：2007-08-16

    申请人： Christopher J. Nelson ,  Kirk B. Bierach

    发明人： Christopher J. Nelson ,  Kirk B. Bierach

    IPC分类号： H04Q5/22

    CPC分类号： G06K7/0008 ,  G06K7/10297

    摘要： A system and method for communicating with contactless IC cards of multiple protocols includes transmitting an IC card polling signal and receiving a data transmission from an IC card. A processor is configured to determine whether or not a data transmission is received in response to the polling signal. The processor is configured to decode the data transmission in real-time if it is received in response to the polling signal. The processor is otherwise configured to first store the received data transmission in a memory and then decode the stored data transmission.

    System and method for interrogation radio-frequency identification
    6.
    发明申请
    System and method for interrogation radio-frequency identification 有权
    用于询问射频识别的系统和方法

    公开(公告)号：US20090045913A1

    公开(公告)日：2009-02-19

    申请号：US11893678

    申请日：2007-08-16

    申请人： Christopher J. Nelson ,  Scott E. Lindley

    发明人： Christopher J. Nelson ,  Scott E. Lindley

    IPC分类号： G06K7/10

    CPC分类号： G06K7/0008 ,  G06K7/10217

    摘要： A system and method for communicating with contactless IC cards of multiple protocols and power levels includes generating a first alternating magnetic field with an interrogator for energizing a proximate IC card and receiving a data transmission from the IC card. A processor of the interrogator is configured to decode the received data transmission. The interrogator then generates a second alternating magnetic field having a different magnetic field strength than the first alternating magnetic field when failing to decode the data transmission being received from the IC card. The processor then attempts to decode a data transmission received from the IC card in response to the second alternating magnetic field.

    摘要翻译： 用于与多个协议和功率电平的非接触式IC卡进行通信的系统和方法包括：用询问器生成第一交变磁场，用于激励邻近的IC卡并从IC卡接收数据传输。 询问器的处理器被配置为对接收的数据传输进行解码。 然后当不能解码从IC卡接收的数据传输时，询问器产生具有与第一交变磁场不同的磁场强度的第二交变磁场。 然后处理器响应于第二交变磁场尝试对从IC卡接收的数据传输进行解码。

    System and method for multi-protocol radio-frequency identification
    8.
    发明申请
    System and method for multi-protocol radio-frequency identification 有权
    多协议射频识别系统和方法

    公开(公告)号：US20090045921A1

    公开(公告)日：2009-02-19

    申请号：US11893679

    申请日：2007-08-16

    申请人： Christopher J. Nelson ,  Kirk B. Bierach

    发明人： Christopher J. Nelson ,  Kirk B. Bierach

    IPC分类号： H04Q5/22

    CPC分类号： G06K7/0008 ,  G06K7/10297

    摘要： A system and method for communicating with contactless IC cards of multiple protocols includes transmitting an IC card polling signal and receiving a data transmission from an IC card. A processor is configured to determine whether or not a data transmission is received in response to the polling signal. The processor is configured to decode the data transmission in real-time if it is received in response to the polling signal. The processor is otherwise configured to first store the received data transmission in a memory and then decode the stored data transmission.

    摘要翻译： 用于与多个协议的非接触IC卡通信的系统和方法包括发送IC卡轮询信号并从IC卡接收数据传输。 处理器被配置为确定响应于轮询信号是否接收到数据传输。 处理器被配置为如果响应于轮询信号而被接收则实时地解码数据传输。 处理器被配置为首先将接收到的数据传输存储在存储器中，然后对存储的数据传输进行解码。