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公开(公告)号：US20140329476A1
公开(公告)日：2014-11-06
申请号：US14258246
申请日：2014-04-22
Inventor： Shintaro YAMAMICHI , Hirokazu HONDA , Masaki WATANABE , Junichi ARITA , Norio OKADA , Jun UENO , Masashi NISHIMOTO , Michitaka KIMURA , Tomohiro NISHIYAMA
CPC classification number: H04W84/18 , H01L2224/45144 , H01L2224/48091 , H01L2224/49111 , H01L2924/00014 , H01L2924/00
Abstract: A compact electronic device as a constituent element of a wireless communication system using a sensor. A first feature of the device is that a first semiconductor chip is bare-chip-mounted over a front surface of a first wiring board in the form of a chip and a second semiconductor chip is bare-chip-mounted over a second wiring board in the form of a chip. A second feature is that a wireless communication unit and a data processing unit which configure a module are separately mounted. A third feature is that the first and second wiring boards are stacked in the board thickness direction to make up the module (electronic device).
Abstract translation: 作为使用传感器的无线通信系统的组成要素的小型电子设备。 该器件的第一个特征是第一半导体芯片以芯片的形式裸地安装在第一布线板的前表面上，并且第二半导体芯片裸地安装在第二布线板上 芯片的形式。 第二特征是分别安装配置模块的无线通信单元和数据处理单元。 第三特征是第一和第二布线板沿板厚度方向堆叠以组成模块（电子设备）。
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公开(公告)号：US20180310529A1
公开(公告)日：2018-11-01
申请号：US16029871
申请日：2018-07-09
Applicant: Renesas Electronics Corporation
Inventor： Takuo Funaya , Tomohiro NISHIYAMA , Hiroki SHIBUYA , Manabu OKAMOTO
CPC classification number: A01K29/005 , A01K11/006 , A61B5/0002 , A61B5/11 , A61D17/00 , G01D11/245 , H04W4/70
Abstract: A method for manufacturing an electronic apparatus functioning as a component of a wireless communication system includes providing a lower part formed with a first concave portion, a second concave portion spaced away from the first concave portion, and a third concave portion which couples the first concave portion and the second concave portion, providing an upper part for sealing the first concave portion, the second concave portion, and the third concave portion formed in the lower part, providing a module unit including a sensor which detects a physical quantity, and a radio communication unit which transmits data based on an output signal from the sensor, providing a battery for supplying power to the module unit, coupling the module unit and the battery by a wiring, and after the coupling the module unit and the battery, arranging the module unit in the first concave portion of the lower part.
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公开(公告)号：US20180342440A1
公开(公告)日：2018-11-29
申请号：US15969835
申请日：2018-05-03
Applicant: Renesas Electronics Corporation
Inventor： Tomohiro NISHIYAMA
IPC: H01L23/492 , H01L25/07 , H01L29/739 , H01L23/053
Abstract: An electronic device has a first bus bar (conductor plate) connected to a first semiconductor device (semiconductor part) having a first power transistor; and a second bus bar (conductor plate) connected to a second semiconductor device (semiconductor part) having a second power transistor. The first and second bus bars have first portions facing each other with an insulating plate interposed therebetween and extending in a Z direction intersecting with an upper surface (main surface) of a board. The first bus bar has a second portion located between the first portion and a terminal (exposed portion) and extending in an X direction away from the second bus bar and a third portion located between the second portion and the terminal and extending in the X direction. An extension distance of the third portion in the Z direction is shorter than an extension distance of the second portion in the X direction.
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Patent Agency Ranking
公开(公告)号：US20180367012A1
公开(公告)日：2018-12-20
申请号：US15563011
申请日：2015-09-14
Applicant: Renesas Electronics Corporation
Inventor： Shinji NISHIZONO , Tadashi SHIMIZU , Tomohiro NISHIYAMA , Norikazu MOTOHASHI
IPC: H02K11/33 , H02M7/537 , H02P27/06 , H01L23/00 , H01L23/528
Abstract: A first semiconductor device having a power transistor for switching is mounted on a power wiring substrate PB1; a semiconductor device PKG6 having a driving circuit for driving the first semiconductor device and a semiconductor device PKG5 having a control circuit for controlling the semiconductor device PKG6 are mounted on a first principal surface of a control wiring substrate PB2; and a semiconductor device PKG4 having a regulator circuit is mounted on a second principal surface of the control wiring substrate PB2. On the first principal surface of the control wiring substrate PB2, the semiconductor device PKG5 and the semiconductor device PKG6 are mounted in a second area out of the second area and a third area adjacent to each other via a first area in which a plurality of holes HC3 are arranged. On the second principal surface of the control wiring substrate PB2, the semiconductor device PKG4 is mounted in a fifth area out of a fourth area positioned opposite the second area and the fifth area positioned opposite the third area.
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公开(公告)号：US20240186224A1
公开(公告)日：2024-06-06
申请号：US18060680
申请日：2022-12-01
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Tomohiro NISHIYAMA , Toshiyuki HATA , Tatsuaki TSUKUDA
IPC: H01L23/498 , H01L23/00 , H01L23/495
CPC classification number: H01L23/49811 , H01L23/4952 , H01L23/49833 , H01L23/49838 , H01L24/18 , H01L24/48 , H01L24/73 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/182
Abstract: Improving a performance of a semiconductor device. A method of manufacturing the semiconductor device, including steps of: forming a first convex portion on a front surface of a chip mounting portion; and mounting a semiconductor chip on the front surface of the chip mounting portion via a conductive adhesive material. Here, the semiconductor chip includes: a main transistor forming portion in which a main transistor is formed; and a sense transistor forming portion in which a sense transistor is formed. Also, in the step for mounting the semiconductor chip on the chip mounting portion, the semiconductor chip is mounted on the front surface of the chip mounting portion such that the sense transistor forming portion of the semiconductor chip overlaps the first convex portion formed on the front surface of the chip mounting portion in the step for forming the first convex portion.
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公开(公告)号：US20240170375A1
公开(公告)日：2024-05-23
申请号：US17993390
申请日：2022-11-23
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Tatsuaki TSUKUDA , Tomohiro NISHIYAMA , Toshiyuki HATA , Koichi HASEGAWA
IPC: H01L23/495 , H01L23/00 , H01L23/31
CPC classification number: H01L23/49575 , H01L23/3107 , H01L23/49562 , H01L24/32 , H01L24/40 , H01L24/48 , H01L24/37 , H01L24/45 , H01L24/73 , H01L2224/32145 , H01L2224/32245 , H01L2224/37147 , H01L2224/40175 , H01L2224/45144 , H01L2224/45147 , H01L2224/48145 , H01L2224/48245 , H01L2224/73265
Abstract: The on-resistance of a semiconductor device is reduced. A package structure composing the semiconductor device includes a die pad, a plurality of leads, a first semiconductor chip having a power transistor and mounted on the die pad, and a second semiconductor chip including a control circuit for controlling the power transistor and mounted on the first semiconductor chip. Here, a source pad of the first semiconductor chip is electrically connected to a first lead and a seventh lead of the plurality of leads via a clip made of a material which is copper as a main component, and the width (and cross-sectional area) of the clip is larger than the width (and diameter) of a wire in plan view.
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公开(公告)号：US20180368262A1
公开(公告)日：2018-12-20
申请号：US15562992
申请日：2015-08-21
Applicant: Renesas Electronics Corporation
Inventor： Norikazu MOTOHASHI , Tomohiro NISHIYAMA , Tadashi SHIMIZU , Shinji NISHIZONO
IPC: H05K1/18 , H05K1/11 , H05K1/14 , H02M7/00 , H02P27/06 , H01L23/31 , H01L23/495 , H02K11/33 , F02M37/08
CPC classification number: H05K1/181 , F02M37/08 , F02M2037/085 , H01L23/3107 , H01L23/49513 , H01L23/4952 , H01L23/49562 , H01L23/49575 , H02K11/33 , H02K2211/03 , H02M7/003 , H02M7/48 , H02P27/06 , H05K1/115 , H05K1/14 , H05K2201/042 , H05K2201/09027 , H05K2201/09063 , H05K2201/10166
Abstract: A plurality of semiconductor devices each including a semiconductor chip having a high-side MOSFET and a semiconductor chip having a low-side MOSFET are mounted on a wiring board (PB1). The wiring board (PB1) includes a power supply wiring WV1 to which a power supply potential is supplied and output wirings WD1, WD2, and WD3 electrically connecting a low-side drain terminal of each of the plurality of semiconductor devices to a plurality of output terminals. A minimum value and a maximum value of a current path width in the power supply wiring WV1 are referred to as a first minimum width and a first maximum width, respectively, and a minimum value and a maximum value of a current path width in the output wirings WD1, WD2, and WD3 are referred to as a second minimum width and a second maximum width, respectively. When the first minimum width is smaller than the second minimum width, the first minimum width is larger than half of the second maximum width, and when the second minimum width is smaller than the first minimum width, the second minimum width is larger than half of the first maximum width.
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公开(公告)号：US20170303389A1
公开(公告)日：2017-10-19
申请号：US15480920
申请日：2017-04-06
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Norikazu MOTOHASHI , Tomohiro NISHIYAMA , Tadashi SHIMIZU , Shinji NISHIZONO
CPC classification number: H05K1/0215 , H05K1/0218 , H05K1/115 , H05K1/116 , H05K5/0065 , H05K9/0039 , H05K2201/0723 , H05K2201/09354 , H05K2201/09618 , H05K2201/09972 , H05K2201/10166 , H05K2201/10409
Abstract: An electronic device has a control board having a plurality of wiring layers, a metal-made housing supporting the control board, and a fixing screw for fixing the control board to the housing through a washer. The control board includes a through hole penetrating from a third surface to a fourth surface, a through electrode formed inside the through hole, and a power system GND pattern formed on any wiring layer of the wiring layers. The power system GND pattern and the housing are electrically coupled through the through electrode, the washer, and the fixing screw.
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