公开(公告)号：US20080315362A1

公开(公告)日：2008-12-25

申请号：US11767147

申请日：2007-06-22

申请人： Robert B. Lempkowski ,  Lih-Tyng Hwang

发明人： Robert B. Lempkowski ,  Lih-Tyng Hwang

IPC分类号： H01L29/93 ,  H01L21/28

CPC分类号： H02N1/006 ,  H01G5/16

摘要： A micro-electro-mechanical system varactor. The varactor includes a substrate, a lower bias conductor partially overlaying the substrate, a first signal conductor partially overlaying the substrate, a dielectric layer at least partially overlaying the first signal conductor, a support structure coupled to the substrate, and a flexible structure coupled to the support structure. The flexible structure is suspended over the substrate, includes an upper bias conductor overlaying at least part of the lower bias conductor and a top conductor overlaying at least part of the first signal conductor, configured to deflect in response to a bias voltage applied between the upper bias conductor and the lower bias conductor, and configured for separation between the top conductor and the dielectric layer by a varying separation distance dependent upon the bias voltage.

摘要翻译： 微机电系统变容二极管。 变容二极管包括衬底，部分地覆盖衬底的下部偏置导体，部分覆盖衬底的第一信号导体，至少部分覆盖第一信号导体的电介质层，耦合到衬底的支撑结构，以及耦合到 支撑结构。 柔性结构悬挂在衬底上，包括覆盖低偏压导体的至少一部分的上偏置导体和覆盖第一信号导体的至少一部分的顶导体，其配置为响应于施加在上 偏置导体和下偏置导体，并且被配置为根据偏置电压在顶部导体和介电层之间分离变化的间隔距离。

公开(公告)号：US07136274B2

公开(公告)日：2006-11-14

申请号：US10975720

申请日：2004-10-28

申请人： Lih-Tyng Hwang ,  Robert B. Lempkowski ,  Li Li

发明人： Lih-Tyng Hwang ,  Robert B. Lempkowski ,  Li Li

IPC分类号： H01G4/228

CPC分类号： H05K1/16 ,  H01G4/40 ,  H05K1/0298 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09236 ,  H05K2201/09672

摘要： An embedded multilayer printed circuit includes a first ground plane (105, 1205, 1405) of a multilayer printed circuit board and an embedded layer. The embedded layer includes a co-planar capacitor (110, 1210, 1410), a distributed inductor (125, 1215, 1415), and a capacitive plate (135, 1220, 1420) circuit. The capacitive plate is a plate of a vertical capacitor (270, 1305, 1505). The embedded layer further includes a node (111, 1225, 1425) of the embedded multilayer printed circuit that is formed by a connection of a first terminal of the co-planar capacitor and a first terminal of the first distributed inductor, and in some embodiments, the first capacitive plate is also connected to the node. A second terminal of one of the co-planar capacitor and the distributed inductor is connected to the first ground plane.

摘要翻译： 嵌入式多层印刷电路包括多层印刷电路板和嵌入层的第一接地平面（105,1205,1405）。 嵌入层包括共面电容器（110,1210,1410），分布式电感器（125,1215,1415）和电容板（135,1220,1420）电路。 电容板是垂直电容器（270,1305,1505）的板。 嵌入层还包括通过共面电容器的第一端子和第一分布式电感器的第一端子的连接形成的嵌入式多层印刷电路的节点（111,1225,1425），并且在一些实施例中 ，第一电容板也连接到节点。 共面电容器和分布式电感器之一的第二端子连接到第一接地层。

公开(公告)号：US07499257B2

公开(公告)日：2009-03-03

申请号：US11767147

申请日：2007-06-22

申请人： Robert B. Lempkowski ,  Lih-Tyng Hwang

发明人： Robert B. Lempkowski ,  Lih-Tyng Hwang

IPC分类号： H01G5/00

CPC分类号： H02N1/006 ,  H01G5/16

摘要： A micro-electro-mechanical system varactor. The varactor includes a substrate, a lower bias conductor partially overlaying the substrate, a first signal conductor partially overlaying the substrate, a dielectric layer at least partially overlaying the first signal conductor, a support structure coupled to the substrate, and a flexible structure coupled to the support structure. The flexible structure is suspended over the substrate, includes an upper bias conductor overlaying at least part of the lower bias conductor and a top conductor overlaying at least part of the first signal conductor, configured to deflect in response to a bias voltage applied between the upper bias conductor and the lower bias conductor, and configured for separation between the top conductor and the dielectric layer by a varying separation distance dependent upon the bias voltage.

摘要翻译： 微机电系统变容二极管。 变容二极管包括衬底，部分地覆盖衬底的下部偏置导体，部分覆盖衬底的第一信号导体，至少部分覆盖第一信号导体的电介质层，耦合到衬底的支撑结构，以及耦合到 支撑结构。 柔性结构悬挂在衬底上，包括覆盖低偏压导体的至少一部分的上偏置导体和覆盖第一信号导体的至少一部分的顶导体，其配置为响应于施加在上 偏置导体和下偏置导体，并且被配置为根据偏置电压在顶部导体和介电层之间分离变化的间隔距离。

公开(公告)号：US4774630A

公开(公告)日：1988-09-27

申请号：US781981

申请日：1985-09-30

申请人： Arnold Reisman ,  Carlton M. Osburn ,  Lih-Tyng Hwang ,  Jagdish Narayan

发明人： Arnold Reisman ,  Carlton M. Osburn ,  Lih-Tyng Hwang ,  Jagdish Narayan

IPC分类号： H01L23/32 ,  G02B6/42 ,  H01L21/60 ,  H01L23/473 ,  H01L23/498 ,  H01R33/76 ,  H05K7/10 ,  H02B1/00

CPC分类号： H01L24/80 ,  G02B6/42 ,  H01L23/473 ,  H01L23/498 ,  H05K7/1061 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025

摘要： Apparatus for mounting a semiconductor device chip and making electrical connections thereto is disclosed. A semiconductor device chip has its backside connected to the surface of a substrate, and its upper surface includes a plurality of electrical pads across the entire surface thereof. A translator chip having a plurality of first electrical contacts disposed generally across the interior portion thereof are in electrical contact with the semiconductor device chip electrical pads, and a plurality of second electrical contacts disposed generally around the perimeter of the translator chip are electrically connected with the electrical terminals in the substrate to which the chip is attached. Heat may be removed from the semiconductor device chip through its backside via cooling channels in the substrate.

摘要翻译： 公开了用于安装半导体器件芯片并与其连接的装置。 半导体器件芯片的背面连接到衬底的表面，并且其上表面在其整个表面上包括多个电焊盘。 具有大致横跨其内部布置的多个第一电触点的转换器芯片与半导体器件芯片电焊垫电接触，并且大体上围绕转换器芯片的周边设置的多个第二电触头与 芯片所连接的基板中的电端子。 可以通过其背面通过衬底中的冷却通道从半导体器件芯片去除热量。

公开(公告)号：US20100287273A1

公开(公告)日：2010-11-11

申请号：US12435921

申请日：2009-05-05

申请人： Irfan Nasir ,  Lih-Tyng Hwang ,  Magdi A. Mohamed ,  Aroon V. Tungare

发明人： Irfan Nasir ,  Lih-Tyng Hwang ,  Magdi A. Mohamed ,  Aroon V. Tungare

IPC分类号： G06F15/173 ,  H04B7/26

CPC分类号： H04W48/18 ,  H04W88/06 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/162 ,  Y02D70/164

摘要： Disclosed is a communications device that monitors the status of its communications links. When more than one communications link is available, an “appropriate” link is selected for use by an application running on the device. The links are continually monitored, and, as circumstances change, the link selection can also change. In some embodiments, a link is “appropriate” when it is available to transfer data and when it satisfies certain “hard” rules set by the application or by a user of the communications device. Some embodiments monitor the behaviour of the communications device and of its user and capture that behaviour in “soft” rules that are applied when selecting an appropriate link and when the hard rules leave the choice open. When multiple links transmit on the same frequency, they may be supported “virtually simultaneously” by time-slicing the actual data transmissions. Unneeded links may be shut down to save battery power.

摘要翻译： 公开了一种监视其通信链路的状态的通信设备。 当有多个通信链路可用时，选择“适当”链接以供在设备上运行的应用程序使用。 链接被不断监视，随着情况的变化，链接选择也可以改变。 在一些实施例中，当链路可用于传输数据时以及当它满足由应用或由通信设备的用户设置的某些“硬”规则时，链路是“适当的”。 一些实施例监视通信设备及其用户的行为，并且在选择适当链接时应用的“软”规则捕获该行为以及当硬规则离开选择时是否被打开。 当多个链路在相同频率上传输时，可以通过对实际的数据传输进行时间分片来“虚拟地同时地”支持它们。 可能关闭不需要的链接以节省电池电量。

公开(公告)号：US07463113B2

公开(公告)日：2008-12-09

申请号：US11276429

申请日：2006-02-28

申请人： Aroon Tungare ,  Manes Eliacin ,  Lih-Tyng Hwang ,  Robert Lempkowski ,  Junhua Liu ,  Jovica Savic

发明人： Aroon Tungare ,  Manes Eliacin ,  Lih-Tyng Hwang ,  Robert Lempkowski ,  Junhua Liu ,  Jovica Savic

IPC分类号： H01P1/10

CPC分类号： H01G5/16 ,  H01G5/011 ,  H01H59/0009

摘要： A first and second capacitor plate are provided (101 and 102). Each capacitor plate has an opening disposed therethrough with the second capacitor plate being disposed substantially opposite the first capacitor plate. A first electrically conductive path interface is then disposed (103) in one of these openings as is at least a second electrically conductive path interface (104).

摘要翻译： 提供第一和第二电容器板（101和102）。 每个电容器板具有穿过其中的开口，其中第二电容器板与第一电容器板大致相对设置。 然后，至少第二导电路径接口（104）将第一导电路径界面（103）设置在这些开口之一中。

公开(公告)号：US5661042A

公开(公告)日：1997-08-26

申请号：US520118

申请日：1995-08-28

申请人： Treliant Fang ,  Lih-Tyng Hwang ,  William M. Williams

发明人： Treliant Fang ,  Lih-Tyng Hwang ,  William M. Williams

IPC分类号： G01R1/073 ,  G01R31/28 ,  H01L21/68 ,  H05K3/32 ,  H01L21/288 ,  H01L21/58 ,  H01L21/60

CPC分类号： H01L21/6835 ,  G01R1/073 ,  G01R31/2863 ,  H01L2224/16 ,  H01L2924/01079 ,  H05K3/323

摘要： A process for using removable Z-axis anisotropically conductive adhesive material (21) which includes water, a matrix resin (23), and conductive spheres (22). The material (21) is suitable for providing temporary contact between electronic devices. In one embodiment, the material (21) is used to temporarily bond a semiconductor wafer (11) to a probe substrate (12) for wafer-level burn-in.

摘要翻译： 一种使用可移除的Z轴各向异性导电粘合剂材料（21）的方法，其包括水，基质树脂（23）和导电球体（22）。 材料（21）适用于在电子设备之间提供临时接触。 在一个实施例中，材料（21）用于将半导体晶片（11）临时粘合到用于晶片级老化的探针衬底（12）。

公开(公告)号：US06906406B2

公开(公告)日：2005-06-14

申请号：US10324533

申请日：2002-12-19

申请人： Lih-Tyng Hwang ,  James E. Drye ,  Shun Meen Kuo

发明人： Lih-Tyng Hwang ,  James E. Drye ,  Shun Meen Kuo

IPC分类号： H01L23/057 ,  H01L23/538 ,  H01L25/065 ,  H01L21/44

CPC分类号： H01L23/5386 ,  H01L23/057 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48137 ,  H01L2224/49171 ,  H01L2224/854 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device for multiple dice is provided that reduces insertion loss and return loss. In an example embodiment, the semiconductor device comprises: a package 20 comprising a mount surface 14 to which dice 61 and 65 are mounted, and a bond pad surface 25 defining at least a first die area 27 and a second die area 29, wherein the second die area 29 is different in form from the first die area 27.

摘要翻译： 提供了一种用于多个骰子的半导体器件，其减少了插入损耗和回波损耗。 在一个示例性实施例中，半导体器件包括：封装件20，其包括安装表面14，芯片61和65被安装到该安装表面14以及限定至少第一管芯区域27和第二管芯区域29的接合焊盘表面25， 第二管芯区域29的形状与第一管芯区域27不同。

公开(公告)号：US5912510A

公开(公告)日：1999-06-15

申请号：US672389

申请日：1996-05-29

申请人： Lih-Tyng Hwang ,  William H. Lytle

发明人： Lih-Tyng Hwang ,  William H. Lytle

IPC分类号： H01L21/60 ,  H01L23/485 ,  H05K3/28 ,  H05K3/32 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H05K3/321 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/81141 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/10674 ,  H05K3/28

摘要： A bonding structure (10) is formed between a first component (12) and a second component (11) to form a semiconductor device. The bonding structure (10) comprises a bump (24) that has a pedestal region (22) and a crown region (23). The crown region (23) is anchored into a well region (13) of a conductive material (16) that is formed on the second component (11).

摘要翻译： 在第一部件（12）和第二部件（11）之间形成接合结构（10）以形成半导体器件。 接合结构（10）包括具有基座区域（22）和冠部区域（23）的凸块（24）。 冠部区域（23）被锚定在形成在第二部件（11）上的导电材料（16）的阱区域（13）中。

公开(公告)号：US5325265A

公开(公告)日：1994-06-28

申请号：US819571

申请日：1992-01-07

申请人： Iwona Turlik ,  Arnold Reisman ,  Deepak Nayak ,  Lih-Tyng Hwang ,  Giora Dishon ,  Scott L. Jacobs ,  Robert F. Darveaux ,  Neil M. Poley

发明人： Iwona Turlik ,  Arnold Reisman ,  Deepak Nayak ,  Lih-Tyng Hwang ,  Giora Dishon ,  Scott L. Jacobs ,  Robert F. Darveaux ,  Neil M. Poley

IPC分类号： H01L23/373 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065 ,  H05K7/20

CPC分类号： H01L24/32 ,  H01L23/3736 ,  H01L23/473 ,  H01L23/5383 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/83051 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351

摘要： A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct heat from the chips to the heat sink.

摘要翻译： 高性能集成电路芯片封装包括：支撑基板，其具有从一个面向其相对面延伸的导体，以及在该支撑基板的相对面上的多层布线基板，用于将安装在其上的芯片彼此连接并连接至导体。 散热器包括在其一个面上的微通道，其中导热垫将散热片的一个面与芯片的暴露的背面连接起来，以提供具有高散热性的高密度芯片封装。 支撑衬底和散热器可以由具有热膨胀匹配硅的材料块形成。 垫子是低熔点焊料，优选纯铟，并且足够厚以吸收热应力，但是足够薄以有效地将热量从芯片传导到散热器。