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公开(公告)号：US09123843B2
公开(公告)日：2015-09-01
申请号：US14492965
申请日：2014-09-22
发明人： Takashi Kyono , Katsushi Akita , Kaoru Shibata , Koji Nishizuka , Kei Fujii
IPC分类号： H01L21/00 , H01L31/0352 , H01L31/0304 , H01L31/09
CPC分类号： H01L31/035236 , H01L31/02963 , H01L31/0304 , H01L31/18 , Y02E10/544
摘要： A semiconductor device includes a semiconductor layer laminate in which a plurality of semiconductor layers are laminated, the semiconductor layer laminate including a light receiving layer, the light receiving layer being grown by a metal-organic vapor phase epitaxy method, the light receiving layer having a cutoff wavelength of more than or equal to 3 μm and less than or equal to 8 μm, the semiconductor device having a dark current density of less than or equal to 1×10−1 A/cm2 when a reverse bias voltage of 60 mV is applied at a temperature of −140° C. Thereby, a semiconductor device which can receive light in a mid-infrared range and has a low dark current is provided.
摘要翻译： 半导体器件包括其中层叠有多个半导体层的半导体层层叠体，所述半导体层层叠体包括受光层，所述光接收层通过金属 - 有机气相外延法生长，所述光接收层具有 截止波长大于或等于3μm且小于或等于8μm时，当反向偏置电压为60mV时，半导体器件的暗电流密度小于或等于1×10-1A / cm 2 在-140℃的温度下施加。因此，提供了能够接收中红外范围并且具有低暗电流的光的半导体器件。
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公开(公告)号：US10024516B2
公开(公告)日：2018-07-17
申请号：US15644293
申请日：2017-07-07
发明人： Takashi Kyono , Hiromi Nakanishi , Hideyuki Ijiri , Kaoru Shibata
IPC分类号： F21V3/02 , F21V15/01 , F21V17/10 , F21Y115/30
摘要： An optical module includes a transmitting member. The transmitting member is fixed to a cap member so as to cover a through-hole. On the assumption that the height of one point on a first surface in a state in which the transmitting member is detached from the cap member is zero and the direction toward the outside of the optical module is a positive direction, the amount of warp that is a difference between the displacement at the central point and the displacement at a standard point, on the first surface, corresponding to a reference point, on the projection image, away from a center of gravity by a particular distance is different between a first geodesic line and a second geodesic line, the displacement being a height of the one point in a direction of the optical axis in a state in which the transmitting member is fixed to the cap member. The transmitting member is joined to the cap member at the first surface or the second surface.
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公开(公告)号：US20180010763A1
公开(公告)日：2018-01-11
申请号：US15644293
申请日：2017-07-07
发明人： Takashi Kyono , Hiromi Nakanishi , Hideyuki Ijiri , Kaoru Shibata
CPC分类号： F21V3/02 , F21V15/01 , F21V17/101 , F21Y2115/30 , H01S5/02216 , H01S5/02248 , H01S5/02296 , H01S5/4012 , H01S5/4093
摘要： An optical module includes a transmitting member. The transmitting member is fixed to a cap member so as to cover a through-hole. On the assumption that the height of one point on a first surface in a state in which the transmitting member is detached from the cap member is zero and the direction toward the outside of the optical module is a positive direction, the amount of warp that is a difference between the displacement at the central point and the displacement at a standard point, on the first surface, corresponding to a reference point, on the projection image, away from a center of gravity by a particular distance is different between a first geodesic line and a second geodesic line, the displacement being a height of the one point in a direction of the optical axis in a state in which the transmitting member is fixed to the cap member. The transmitting member is joined to the cap member at the first surface or the second surface.
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公开(公告)号：US09680040B2
公开(公告)日：2017-06-13
申请号：US14784817
申请日：2014-04-16
发明人： Kaoru Shibata , Katsushi Akita , Kei Fujii , Takashi Ishizuka
IPC分类号： H01L33/00 , H01L31/0352 , H01S5/343 , H01L27/146 , H01L31/0304 , H01L31/109 , H01L31/18 , H01S5/042 , H01S5/30 , H01S5/34
CPC分类号： H01L31/035236 , H01L27/1464 , H01L27/14652 , H01L31/03046 , H01L31/109 , H01L31/1844 , H01S5/0425 , H01S5/305 , H01S5/3422 , H01S5/34306 , H01S2301/173
摘要： A semiconductor device and the like having high quantum efficiency or high sensitivity in a near-infrared to infrared region is provided. The semiconductor device includes: a substrate; a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a layer a and a layer b; and a crystal-adjusting layer disposed between the substrate and the multiple quantum well structure. The crystal-adjusting layer includes a first adjusting layer which is made of the same material as the substrate and is in contact with the substrate, and a second adjusting layer which is made of the same material as the layer a or the layer b of the multiple quantum well structure and is in contact with the multiple quantum well structure.
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5.发明申请SEMICONDUCTOR LAYERED STRUCTURE, METHOD FOR PRODUCING SEMICONDUCTOR LAYERED STRUCTURE, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE 有权半导体层结构，半导体层结构的制造方法及半导体器件的制造方法公开(公告)号：US20160351742A1
公开(公告)日：2016-12-01
申请号：US15114001
申请日：2015-01-19
发明人： Katsushi Akita , Kei Fujii , Takashi Kyono , Koji Nishizuka , Kaoru Shibata
IPC分类号： H01L31/109 , H01L31/0224 , H01L31/0304 , H01L31/18 , H01L31/0352 , H01L31/0392
CPC分类号： H01L31/109 , C30B29/40 , H01L21/02387 , H01L21/02463 , H01L21/02466 , H01L21/02507 , H01L21/02546 , H01L21/02549 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L29/06 , H01L31/022408 , H01L31/03046 , H01L31/035236 , H01L31/0392 , H01L31/105 , H01L31/1844 , Y02E10/544 , Y02P70/521
摘要： A semiconductor layered structure includes a substrate formed of a III-V compound semiconductor, a buffer layer disposed on and in contact with the substrate and formed of a III-V compound semiconductor, and a quantum well layer disposed on and in contact with the buffer layer and including a plurality of component layers formed of III-V compound semiconductors. The substrate has a diameter of 55 mm or more. At least one of the component layers is formed of a mixed crystal of three or more elements. When the compound semiconductor forming the substrate has a lattice constant d1, the compound semiconductor forming the buffer layer has a lattice constant d2, and the compound semiconductors forming the quantum well layer have an average lattice constant d3, (d2−d1)/d1 is −3×10−3 or more and 3×10−3 or less, and (d3−d1)/d1 is −3×10−3 or more and 3×10−3 or less.
摘要翻译： 半导体层状结构包括由III-V族化合物半导体形成的衬底，与衬底配置并与衬底接触并由III-V族化合物半导体形成的缓冲层，以及设置在缓冲层上并与缓冲层接触的量子阱层 并且包括由III-V族化合物半导体形成的多个成分层。 基板的直径为55mm以上。 组分层中的至少一个由三个或更多个元素的混合晶体形成。 当构成基板的化合物半导体具有晶格常数d1时，构成缓冲层的化合物半导体的晶格常数为d2，形成量子阱层的化合物半导体的平均晶格常数为d3，（d2-d1）/ d1为 -3×10-3以上3×10-3以下，（d3-d1）/ d1为-3×10-3以上且3×10-3以下。
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公开(公告)号：US09887310B2
公开(公告)日：2018-02-06
申请号：US15114001
申请日：2015-01-19
发明人： Katsushi Akita , Kei Fujii , Takashi Kyono , Koji Nishizuka , Kaoru Shibata
IPC分类号： H01L31/109 , H01L31/02 , H01L21/18 , H01L21/02 , H01L29/06 , C30B29/40 , H01L31/0304 , H01L31/0352 , H01L31/105 , H01L31/0224 , H01L31/0392 , H01L31/18
CPC分类号： H01L31/109 , C30B29/40 , H01L21/02387 , H01L21/02463 , H01L21/02466 , H01L21/02507 , H01L21/02546 , H01L21/02549 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L29/06 , H01L31/022408 , H01L31/03046 , H01L31/035236 , H01L31/0392 , H01L31/105 , H01L31/1844 , Y02E10/544 , Y02P70/521
摘要： A semiconductor layered structure includes a substrate formed of a III-V compound semiconductor, a buffer layer disposed on and in contact with the substrate and formed of a III-V compound semiconductor, and a quantum well layer disposed on and in contact with the buffer layer and including a plurality of component layers formed of III-V compound semiconductors. The substrate has a diameter of 55 mm or more. At least one of the component layers is formed of a mixed crystal of three or more elements. When the compound semiconductor forming the substrate has a lattice constant d1, the compound semiconductor forming the buffer layer has a lattice constant d2, and the compound semiconductors forming the quantum well layer have an average lattice constant d3, (d2−d1)/d1 is −3×10−3 or more and 3×10−3 or less, and (d3−d1)/d1 is −3×10−3 or more and 3×10−3 or less.
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公开(公告)号：US09773932B2
公开(公告)日：2017-09-26
申请号：US15028225
申请日：2014-08-18
发明人： Kei Fujii , Koji Nishizuka , Takashi Kyono , Kaoru Shibata , Katsushi Akita
IPC分类号： H01L21/00 , H01L31/00 , H01L31/0352 , H01L21/02 , H01L31/0304 , H01L31/18
CPC分类号： H01L31/035236 , H01L21/02392 , H01L21/02461 , H01L21/02463 , H01L21/02466 , H01L21/02507 , H01L21/02546 , H01L21/0262 , H01L31/03042 , H01L31/03046 , H01L31/1832 , Y02E10/544 , Y02P70/521
摘要： An epitaxial wafer which allows manufacture of a photodiode having suppressed dark current and ensured sensitivity, and a method for manufacturing the epitaxial wafer, are provided. The epitaxial wafer of the present invention includes: a III-V semiconductor substrate; and a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a first layer and a second layer. The total concentration of elements contained as impurities in the multiple quantum well structure is less than or equal to 5×1015 cm−3.
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8.发明授权公开(公告)号：US09698287B2
公开(公告)日：2017-07-04
申请号：US14260110
申请日：2014-04-23
发明人： Kei Fujii , Kaoru Shibata , Katsushi Akita
IPC分类号： H01L31/105 , H01L31/0352 , H01L31/0304 , H01L31/18 , H01L21/02
CPC分类号： H01L31/035236 , H01L21/02389 , H01L21/0243 , H01L21/02433 , H01L21/02458 , H01L21/02463 , H01L21/02466 , H01L21/02507 , H01L21/02543 , H01L21/02587 , H01L21/0262 , H01L31/03046 , H01L31/105 , H01L31/1844 , Y02E10/544 , Y02P70/521
摘要： An epitaxial wafer of the present invention includes a substrate composed of a III-V compound semiconductor, a multiple quantum well structure composed of a III-V compound semiconductor and located on the substrate, and a top layer composed of a III-V compound semiconductor and located on the multiple quantum well structure. The substrate has a plane orientation of (100) and an off angle of −0.030° or more and +0.030° or less, and a surface of the top layer has a root-mean-square roughness of less than 10 nm.
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公开(公告)号：US20170040477A1
公开(公告)日：2017-02-09
申请号：US15304805
申请日：2014-12-17
发明人： Suguru Arikata , Takashi Kyono , Koji Nishizuka , Kaoru Shibata , Katsushi Akita
IPC分类号： H01L31/0352 , H01L31/18 , H01L31/0224 , H01L31/0216 , H01L31/0304 , H01L31/109
CPC分类号： H01L31/035236 , H01L31/02161 , H01L31/022408 , H01L31/03042 , H01L31/03046 , H01L31/109 , H01L31/1844 , Y02E10/544
摘要： A semiconductor layered structure according to the present invention includes a substrate formed of a III-V compound semiconductor; and semiconductor layers disposed on the substrate and formed of III-V compound semiconductors. The substrate has a majority-carrier-generating impurity concentration of 1×1017 cm−3 or more and 2×1020 cm−3 or less, and the impurity has an activation ratio of 30% or more.
摘要翻译： 根据本发明的半导体层状结构包括由III-V族化合物半导体形成的衬底; 以及设置在基板上并由III-V族化合物半导体形成的半导体层。 基板的多数载流子产生杂质浓度为1×1017cm-3以上且2×1020cm-3以下，杂质的活化率为30％以上。
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公开(公告)号：US20160247951A1
公开(公告)日：2016-08-25
申请号：US15028225
申请日：2014-08-18
发明人： Kei Fujii , Koji Nishizuka , Takashi Kyono , Kaoru Shibata , Katsushi Akita
IPC分类号： H01L31/0352 , H01L31/0304 , H01L31/18 , H01L21/02
CPC分类号： H01L31/035236 , H01L21/02392 , H01L21/02461 , H01L21/02463 , H01L21/02466 , H01L21/02507 , H01L21/02546 , H01L21/0262 , H01L31/03042 , H01L31/03046 , H01L31/1832 , Y02E10/544 , Y02P70/521
摘要： An epitaxial wafer which allows manufacture of a photodiode having suppressed dark current and ensured sensitivity, and a method for manufacturing the epitaxial wafer, are provided. The epitaxial wafer of the present invention includes: a III-V semiconductor substrate; and a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a first layer and a second layer. The total concentration of elements contained as impurities in the multiple quantum well structure is less than or equal to 5×1015 cm−3.
摘要翻译： 提供了允许制造抑制暗电流并确保灵敏度的光电二极管的外延晶片以及制造外延晶片的方法。 本发明的外延晶片包括：III-V族半导体衬底; 以及设置在所述衬底上的多量子阱结构，并且包括多对第一层和第二层。 在多量子阱结构中作为杂质含有的元素的总浓度小于或等于5×1015cm-3。
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