公开(公告)号：US6159858A

公开(公告)日：2000-12-12

申请号：US884165

申请日：1997-06-27

申请人： Sadahiro Kishii ,  Ko Nakamura ,  Yoshihiro Arimoto ,  Akiyoshi Hatada ,  Rintaro Suzuki ,  Naruo Ueda ,  Kenzo Hanawa

发明人： Sadahiro Kishii ,  Ko Nakamura ,  Yoshihiro Arimoto ,  Akiyoshi Hatada ,  Rintaro Suzuki ,  Naruo Ueda ,  Kenzo Hanawa

IPC分类号： C03C19/00 ,  C09G1/02 ,  C09K3/14 ,  C09K13/04 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/302

CPC分类号： C09G1/02 ,  C03C19/00 ,  C09K3/1409 ,  C09K3/1463 ,  C09K3/1472 ,  C09K13/04 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/31053 ,  H01L21/3212

摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.

摘要翻译： 浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。 此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

公开(公告)号：US5877089A

公开(公告)日：1999-03-02

申请号：US14246

申请日：1998-01-27

申请人： Sadahiro Kishii ,  Akiyoshi Hatada ,  Rintaro Suzuki ,  Hiroshi Horie ,  Yoshihiro Arimoto ,  Ko Nakamura

发明人： Sadahiro Kishii ,  Akiyoshi Hatada ,  Rintaro Suzuki ,  Hiroshi Horie ,  Yoshihiro Arimoto ,  Ko Nakamura

IPC分类号： C09G1/02 ,  C09K3/14 ,  H01L21/3105 ,  H01L21/463

CPC分类号： H01L21/31053 ,  C09G1/02 ,  C09K3/1463 ,  H01L21/463

摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.

摘要翻译： 浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。 此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

公开(公告)号：US5763325A

公开(公告)日：1998-06-09

申请号：US674507

申请日：1996-07-02

申请人： Sadahiro Kishii ,  Akiyoshi Hatada ,  Rintaro Suzuki ,  Hiroshi Horie ,  Yoshihiro Arimoto ,  Ko Nakamura

发明人： Sadahiro Kishii ,  Akiyoshi Hatada ,  Rintaro Suzuki ,  Hiroshi Horie ,  Yoshihiro Arimoto ,  Ko Nakamura

IPC分类号： C09G1/02 ,  C09K3/14 ,  H01L21/3105 ,  H01L21/463

CPC分类号： H01L21/31053 ,  C09G1/02 ,  C09K3/1463 ,  H01L21/463

摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.

摘要翻译： 浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。 此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

公开(公告)号：US5562529A

公开(公告)日：1996-10-08

申请号：US131949

申请日：1993-10-08

申请人： Sadahiro Kishii ,  Yoshihiro Arimoto ,  Hiroshi Horie ,  Fumitoshi Sugimoto

发明人： Sadahiro Kishii ,  Yoshihiro Arimoto ,  Hiroshi Horie ,  Fumitoshi Sugimoto

IPC分类号： B24B37/013 ,  B24B49/10 ,  B24B1/00 ,  B24B7/16

CPC分类号： B24B37/013 ,  B24B49/10 ,  Y10S451/908

摘要： An apparatus and method for polishing a semiconductor wafer. A polisher includes a supporting plate having a conductive film and a polishing cloth formed on the conductive film of the supporting plate. The polishing cloth has a plurality of openings to expose the conductive film. A wafer holder has a conductive wafer holding surface to hold a semiconductor wafer having current detective patterns and an insulating film covering the current detective patterns. A polishing slurry supply device supplies a polishing slurry including ions to either the polishing cloth or the semiconductor wafer. A current detecting device, connected to the supporting plate and the wafer holder, detects a magnitude of a current flowing across the supporting plate and the wafer holder through the conductive wafer holding surface, the semiconductor wafer held by the wafer holder, the current detective patterns of the semiconductor wafer, the polishing slurry filled in the openings of the polishing cloth, and the conductive film.

摘要翻译： 一种用于抛光半导体晶片的装置和方法。 抛光机包括具有导电膜的支撑板和形成在支撑板的导电膜上的抛光布。 抛光布具有多个开口以露出导电膜。 晶片保持器具有导电晶片保持表面，以保持具有电流检测图案的半导体晶片和覆盖当前检测图案的绝缘膜。 研磨浆料供给装置将包含离子的研磨浆料供给到研磨布或半导体晶片。 连接到支撑板和晶片保持器的电流检测装置检测通过导电晶片保持表面流过支撑板和晶片保持器的电流的大小，由晶片保持器保持的半导体晶片，当前的检测模式 的半导体晶片，填充在抛光布的开口中的抛光浆料和导电膜。

公开(公告)号：US6114247A

公开(公告)日：2000-09-05

申请号：US884549

申请日：1997-06-27

申请人： Ko Nakamura ,  Sadahiro Kishii ,  Yoshihiro Arimoto

发明人： Ko Nakamura ,  Sadahiro Kishii ,  Yoshihiro Arimoto

IPC分类号： B24B53/017 ,  B24D11/00 ,  B24D13/12 ,  C09G1/02 ,  H01L21/02 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/302

CPC分类号： B24B53/013 ,  B24B37/044 ,  B24B53/017 ,  C09G1/02 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/31053 ,  H01L21/3212

摘要： A method of fabricating a semiconductor device includes a step of polishing a surface of a substrate by a chemical mechanical polishing process conducted on a polishing cloth by a slurry. The polishing is conducted so that projections having a height of about 30 .mu.m or less are formed on the polishing cloth with an interval of about 55 .mu.m or less as a result of the polishing.

摘要翻译： 制造半导体器件的方法包括通过在抛光布上通过浆料进行的化学机械抛光工艺来抛光衬底的表面的步骤。 进行研磨，由此抛光的结果，在研磨布上以约55μm以下的间隔形成高度约30μm以下的凸起。

公开(公告)号：US5624300A

公开(公告)日：1997-04-29

申请号：US676663

申请日：1996-07-10

申请人： Sadahiro Kishii ,  Yoshihiro Arimoto

发明人： Sadahiro Kishii ,  Yoshihiro Arimoto

IPC分类号： B24B37/013 ,  B24B49/10 ,  B24B1/00 ,  B24B7/16

CPC分类号： B24B37/013 ,  B24B49/10 ,  Y10S451/908

摘要： For providing a method for polishing in which it is possible to polish a substance uniformly over a whole surface of a wafer without observing the polished surface of the wafer halfway through polishing, a wafer with current detective patterns formed of conductors directly contacted with a semiconductor substrate, and an insulating film covering the current detective patterns is held by a wafer holder with conductivity, and the insulating film is polished by a polisher in which a supporting plate with conductivity is exposed in openings through a polishing cloth while supplying a polishing slurry containing ions.

摘要翻译： 为了提供抛光方法，其中可以在晶片的整个表面上均匀地抛光物质，而不通过抛光中途观察晶片的抛光表面，具有由与半导体基板直接接触的导体形成的电流检测图案的晶片 并且覆盖电流检测图案的绝缘膜由具有导电性的晶片保持器保持，并且绝缘膜由抛光机抛光，其中通过抛光布将具有导电性的支撑板暴露在开口中，同时提供含有离子的抛光浆料 。

公开(公告)号：US07064038B2

公开(公告)日：2006-06-20

申请号：US10754577

申请日：2004-01-12

申请人： Hiroshi Kudo ,  Junko Naganuma ,  Sadahiro Kishii

发明人： Hiroshi Kudo ,  Junko Naganuma ,  Sadahiro Kishii

IPC分类号： H01L21/336 ,  H01L21/338 ,  H01L21/337 ,  H01L21/44

CPC分类号： H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606

摘要： The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.

公开(公告)号：US20110187002A1

公开(公告)日：2011-08-04

申请号：US13019509

申请日：2011-02-02

申请人： Sadahiro Kishii ,  Tsuyoshi Kanki ,  Yoshihiro Nakata ,  Yasushi Kobayashi ,  Masato Tanaka ,  Akio Rokugawa

发明人： Sadahiro Kishii ,  Tsuyoshi Kanki ,  Yoshihiro Nakata ,  Yasushi Kobayashi ,  Masato Tanaka ,  Akio Rokugawa

IPC分类号： H01L23/28 ,  H01L21/56

CPC分类号： H01L23/488 ,  H01L24/18 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/03

摘要： A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.

摘要翻译： 支撑基板包括位于第一表面的高度之上的第一表面和第二表面。 芯片安装在第一个表面上。 第一绝缘膜设置在每个芯片上。 第一导电插头连接到延伸穿过每个第一绝缘膜的芯片。 由树脂填充的填充材料填充芯片之间的空间。 布线布置在第一绝缘膜和用于互连不同芯片的填充材料之上。 第二表面，第一绝缘膜的上表面和填充材料的上表面位于同一水平。

公开(公告)号：US07951686B2

公开(公告)日：2011-05-31

申请号：US12708519

申请日：2010-02-18

申请人： Sadahiro Kishii ,  Hirofumi Watatani ,  Masanori Terahara ,  Ryo Tanabe ,  Kaina Suzuki ,  Shigeo Satoh

发明人： Sadahiro Kishii ,  Hirofumi Watatani ,  Masanori Terahara ,  Ryo Tanabe ,  Kaina Suzuki ,  Shigeo Satoh

IPC分类号： H01L21/76

CPC分类号： H01L29/045 ,  H01L21/76232 ,  H01L29/7846

摘要： A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.

摘要翻译： 沟槽形成在半导体衬底的表面层中，沟槽围绕有源区。 在半导体器件上沉积由绝缘材料制成的下绝缘膜，下绝缘膜填充沟槽的下部区域并在上部区域留下空的空间。 在其上具有拉伸应力的由绝缘材料制成的上绝缘膜沉积在下绝缘膜上，上绝缘膜填充留在上部空间中的空白空间。 去除沉积在半导体衬底上而不是在沟槽中的上绝缘膜和下绝缘膜。

公开(公告)号：US07701016B2

公开(公告)日：2010-04-20

申请号：US11541782

申请日：2006-10-03

申请人： Sadahiro Kishii ,  Hirofumi Watatani ,  Masanori Terahara ,  Ryo Tanabe ,  Kaina Suzuki ,  Shigeo Satoh

发明人： Sadahiro Kishii ,  Hirofumi Watatani ,  Masanori Terahara ,  Ryo Tanabe ,  Kaina Suzuki ,  Shigeo Satoh

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/045 ,  H01L21/76232 ,  H01L29/7846

摘要： A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulating film. The upper insulating film has therein a stress generating tensile strain in a surface layer of the active region.

摘要翻译： 在半导体衬底的表面层中形成有围绕有源区的沟槽。 由绝缘材料制成的下绝缘膜填充沟槽的下部区域。 上绝缘膜填充下绝缘膜上方的沟槽的区域。 上部绝缘膜在其中具有在有源区的表面层中的应力产生拉伸应变。