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公开(公告)号：US07957158B2
公开(公告)日：2011-06-07
申请号：US11928782
申请日：2007-10-30
Applicant: Sadamichi Takakusaki , Noriaki Sakamoto , Katsuyoshi Mino
Inventor： Sadamichi Takakusaki , Noriaki Sakamoto , Katsuyoshi Mino
IPC: H05K7/10
CPC classification number: H01L23/49531 , H01L21/565 , H01L23/49575 , H01L23/49811 , H01L24/45 , H01L24/48 , H01L2224/05554 , H01L2224/451 , H01L2224/48091 , H01L2224/48472 , H01L2224/73265 , H01L2924/00014 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H05K1/0203 , H05K1/056 , H05K3/284 , H05K2201/1034 , H05K2201/10924 , H05K2203/049 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
Abstract: A circuit device having improved packaging density is provided. A circuit device of the present invention includes: a circuit board having its surface covered with an insulating layer; conductive patterns formed on a surface of the insulating layer; circuit elements electrically connected to the conductive patterns; and leads connected to pads formed of the conductive patterns. Furthermore, a control element is fixed to an upper surface of a land part formed of a part of a lead, and a back surface of the land part is spaced apart from an upper surface of the circuit board.
Abstract translation: 提供了具有改进的包装密度的电路装置。 本发明的电路装置包括：电路板，其表面被绝缘层覆盖; 形成在绝缘层的表面上的导电图案; 电连接到导电图案的电路元件; 并且连接到由导电图案形成的焊盘的引线。 此外，控制元件固定到由引线的一部分形成的台面部的上表面，并且台肩部的后表面与电路板的上表面间隔开。
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公开(公告)号：US08203848B2
公开(公告)日：2012-06-19
申请号：US12065001
申请日：2006-08-30
Applicant: Sadamichi Takakusaki , Noriaki Sakamoto
Inventor： Sadamichi Takakusaki , Noriaki Sakamoto
IPC: H01R9/00
CPC classification number: H01L23/49861 , H01L23/3672 , H01L23/3735 , H01L24/45 , H01L24/48 , H01L25/16 , H01L2224/32225 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2924/00014 , H01L2924/12041 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H05K1/0203 , H05K1/056 , H05K3/284 , H05K2201/1034 , H05K2201/1053 , H05K2201/10969 , Y10T29/49139 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
Abstract: Provided is a simplified structure of a circuit device in which a power element generating a large amount of heat is incorporated. The circuit device according to the present invention includes: a circuit board whose surface is covered with an insulating layer; a conductive pattern formed on the surface of the insulating layer; a circuit element electrically connected to the conductive pattern; and a lead connected to a pad formed of the conductive pattern. Furthermore, a power element is fixed to the top surface of a land portion formed of a part of the lead. Accordingly, the land portion serves as a heat sink, thereby contributing to heat dissipation.
Abstract translation: 提供了其中并入产生大量热量的功率元件的电路装置的简化结构。 根据本发明的电路装置包括：表面被绝缘层覆盖的电路板; 形成在所述绝缘层的表面上的导电图案; 电连接到所述导电图案的电路元件; 以及连接到由导电图案形成的焊盘的引线。 此外，功率元件固定到由引线的一部分形成的接地部的顶表面。 因此，陆部用作散热器，从而有助于散热。
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公开(公告)号：US07936569B2
公开(公告)日：2011-05-03
申请号：US11307283
申请日：2006-01-30
Applicant: Sadamichi Takakusaki , Noriaki Sakamoto , Motoichi Nezu , Yusuke Igarashi
Inventor： Sadamichi Takakusaki , Noriaki Sakamoto , Motoichi Nezu , Yusuke Igarashi
IPC: H05K7/00
CPC classification number: H05K3/341 , H01L24/83 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2224/83 , H01L2924/01322 , H01L2924/01327 , H01L2924/14 , H01L2924/15787 , H01L2924/19105 , H01L2924/30107 , H05K3/243 , H05K3/244 , H05K3/284 , H05K3/3463 , H05K2201/0391 , H05K2201/10969 , Y02P70/613 , Y10T29/4913 , Y10T29/49155 , H01L2924/00014 , H01L2924/00
Abstract: In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu/Sn alloy layer having poor soldering properties is not generated but a Ni/Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.
Abstract translation: 在作为本发明的电路装置的混合集成电路装置中，在基板的表面上形成包括焊盘的导电图案。 由于在其上安装散热器，所以形成第一焊盘相对较大。 第二焊盘是固定芯片部件或小信号晶体管的小焊盘。 在本发明中，在第一焊盘的表面上形成由镍制成的镀膜。 因此，第一焊盘和焊料不会彼此接触。 因此，不会产生焊接性差的Cu / Sn合金层，而是产生焊接性优异的Ni / Sn合金层。 因此，抑制熔融焊料中的沉陷的发生。
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公开(公告)号：US20090129038A1
公开(公告)日：2009-05-21
申请号：US12065001
申请日：2006-08-30
Applicant: Sadamichi Takakusaki , Noriaki Sakamoto
Inventor： Sadamichi Takakusaki , Noriaki Sakamoto
CPC classification number: H01L23/49861 , H01L23/3672 , H01L23/3735 , H01L24/45 , H01L24/48 , H01L25/16 , H01L2224/32225 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2924/00014 , H01L2924/12041 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H05K1/0203 , H05K1/056 , H05K3/284 , H05K2201/1034 , H05K2201/1053 , H05K2201/10969 , Y10T29/49139 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
Abstract: Provided is a simplified structure of a circuit device in which a power element generating a large amount of heat is incorporated. The circuit device according to the present invention includes: a circuit board whose surface is covered with an insulating layer; a conductive pattern formed on the surface of the insulating layer; a circuit element electrically connected to the conductive pattern; and a lead connected to a pad formed of the conductive pattern. Furthermore, a power element is fixed to the top surface of a land portion formed of a part of the lead. Accordingly, the land portion serves as a heat sink, thereby contributing to heat dissipation.
Abstract translation: 提供了其中并入产生大量热量的功率元件的电路装置的简化结构。 根据本发明的电路装置包括：表面被绝缘层覆盖的电路板; 形成在所述绝缘层的表面上的导电图案; 电连接到所述导电图案的电路元件; 以及连接到由导电图案形成的焊盘的引线。 此外，功率元件固定到由引线的一部分形成的接地部的顶表面。 因此，陆部用作散热器，从而有助于散热。
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公开(公告)号：US20070205017A1
公开(公告)日：2007-09-06
申请号：US11307283
申请日：2006-01-30
Applicant: Sadamichi Takakusaki , Noriaki Sakamoto , Motoichi Nezu , Yusuke Igarashi
Inventor： Sadamichi Takakusaki , Noriaki Sakamoto , Motoichi Nezu , Yusuke Igarashi
CPC classification number: H05K3/341 , H01L24/83 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2224/83 , H01L2924/01322 , H01L2924/01327 , H01L2924/14 , H01L2924/15787 , H01L2924/19105 , H01L2924/30107 , H05K3/243 , H05K3/244 , H05K3/284 , H05K3/3463 , H05K2201/0391 , H05K2201/10969 , Y02P70/613 , Y10T29/4913 , Y10T29/49155 , H01L2924/00014 , H01L2924/00
Abstract: In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu/Sn alloy layer having poor soldering properties is not generated but a Ni/Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.
Abstract translation: 在作为本发明的电路装置的混合集成电路装置中，在基板的表面上形成包括焊盘的导电图案。 由于在其上安装散热器，所以形成第一焊盘相对较大。 第二焊盘是固定芯片部件或小信号晶体管的小焊盘。 在本发明中，在第一焊盘的表面上形成由镍制成的镀膜。 因此，第一焊盘和焊料不会彼此接触。 因此，不会产生焊接性差的Cu / Sn合金层，而是产生焊接性优异的Ni / Sn合金层。 因此，抑制熔融焊料中的沉陷的发生。
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Patent Agency Ranking
公开(公告)号：US20070221704A1
公开(公告)日：2007-09-27
申请号：US11307278
申请日：2006-01-30
Applicant: Sadamichi Takakusaki , Noriaki Sakamoto , Motoichi Nezu , Yusuke Igarashi
Inventor： Sadamichi Takakusaki , Noriaki Sakamoto , Motoichi Nezu , Yusuke Igarashi
IPC: A47J36/02
CPC classification number: H05K3/3484 , B23K35/025 , B23K35/262 , B23K35/362 , H01L2224/45124 , H01L2224/48091 , H01L2224/48472 , H01L2224/73265 , H01L2224/92247 , H01L2924/01322 , H01L2924/19105 , H01L2924/30107 , H05K3/341 , H05K2201/10969 , H01L2924/00014 , H01L2924/00
Abstract: A method of manufacturing a circuit device of the present invention comprises the steps of: forming a conductive pattern including a first pad and a second pad on the surface of a substrate; applying a solder paste to the surface of the first pad and then thermally melting the solder paste, thus forming solder; fixing a circuit element to the second pad; and fixing a circuit element to the first pad with the solder therebetween. Furthermore, a flux constituting the solder paste contains sulfur. Since the sulfur is mixed into the solder paste, surface tension of the solder paste is lowered; accordingly occurrence of sink is suppressed.
Abstract translation: 制造本发明的电路器件的方法包括以下步骤：在衬底的表面上形成包括第一焊盘和第二焊盘的导电图案; 将焊膏施加到第一焊盘的表面，然后热熔化焊膏，从而形成焊料; 将电路元件固定到所述第二焊盘; 以及将电路元件固定到第一焊盘上，其间具有焊料。 此外，构成锡膏的焊剂含有硫。 由于硫被混合到焊膏中，焊膏的表面张力降低; 因此抑制了汇的发生。
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公开(公告)号：US20070193027A1
公开(公告)日：2007-08-23
申请号：US11622198
申请日：2007-01-11
Applicant: Sadamichi Takakusaki , Noriaki Sakamoto
Inventor： Sadamichi Takakusaki , Noriaki Sakamoto
IPC: H01L23/495
CPC classification number: H01L23/49537 , H01L21/565 , H01L23/49531 , H01L23/49568 , H01L24/45 , H01L24/48 , H01L2224/05554 , H01L2224/451 , H01L2224/48091 , H01L2224/73265 , H01L2924/14 , H01L2924/181 , H01L2924/19105 , H01L2924/30107 , H05K1/056 , H05K3/0052 , H05K3/3405 , H05K2201/1034 , H05K2201/10924 , Y10T29/49121 , Y10T29/49126 , Y10T29/4913 , Y10T29/49133 , Y10T29/49165 , H01L2924/00014 , H01L2924/00
Abstract: The method of the present invention includes a first step of preparing a substrate in which a plurality of circuit boards are integrally connected to one another, each of the circuit boards having conductive patterns which include pads formed on a surface of the circuit board; a second step of electrically connecting circuit elements to the respective conductive patterns on each of the circuit boards; a third step of positioning ends of leads above the respective pads by superposing a lead frame including the plurality of leads on the substrate, and fixing the leads to the pads; and a fourth step of separating the circuit boards from the substrate in a state where the leads are fixed to the respective pads on each of the circuit boards, and thus separating the leads from the lead frame.
Abstract translation: 本发明的方法包括：制备其中多个电路板彼此一体地连接的基板的第一步骤，每个电路板具有包括形成在电路板的表面上的焊盘的导电图案; 将电路元件电连接到每个电路板上的各个导电图案的第二步骤; 第三步骤，通过将包括所述多个引线的引线框叠置在所述基板上，并将所述引线固定到所述焊盘，来将引线的端部定位在相应的焊盘之上; 以及在将引线固定到每个电路板上的各个焊盘的状态下将电路板与基板分离的第四步骤，从而将引线与引线框架分离。
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公开(公告)号：US20090135572A1
公开(公告)日：2009-05-28
申请号：US12064996
申请日：2006-08-30
Applicant: Sadamichi Takakusaki , Noriaki Sakamoto
Inventor： Sadamichi Takakusaki , Noriaki Sakamoto
CPC classification number: H01L25/162 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73215 , H01L2224/73265 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/19105 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H05K1/056 , H05K1/142 , H05K3/284 , H05K3/4046 , H05K2201/09554 , H05K2201/10287 , H05K2201/1034 , H05K2201/10924 , Y10T29/5313 , H01L2924/00 , H01L2224/48247 , H01L2924/00014 , H01L2924/00012
Abstract: Provided is a circuit device in which an electronic circuit to be incorporated therein operates stably. A hybrid integrated circuit device includes multiple circuit boards which are disposed on approximately the same plane. An electronic circuit including a conductive pattern and a circuit element is formed on each top surface of the circuit boards. Furthermore, these circuit boards are integrally supported by a sealing resin. Moreover, a lead connected to the electronic circuit formed on the surface of the circuit board is led out from the sealing resin to the outside.
Abstract translation: 提供一种其中并入其中的电子电路稳定地工作的电路装置。 混合集成电路装置包括设置在大致相同平面上的多个电路板。 在电路板的每个顶表面上形成包括导电图案和电路元件的电子电路。 此外，这些电路板由密封树脂一体地支撑。 此外，连接到形成在电路板表面上的电子电路的引线从密封树脂引出到外部。
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公开(公告)号：US07521290B2
公开(公告)日：2009-04-21
申请号：US11622198
申请日：2007-01-11
Applicant: Sadamichi Takakusaki , Noriaki Sakamoto
Inventor： Sadamichi Takakusaki , Noriaki Sakamoto
CPC classification number: H01L23/49537 , H01L21/565 , H01L23/49531 , H01L23/49568 , H01L24/45 , H01L24/48 , H01L2224/05554 , H01L2224/451 , H01L2224/48091 , H01L2224/73265 , H01L2924/14 , H01L2924/181 , H01L2924/19105 , H01L2924/30107 , H05K1/056 , H05K3/0052 , H05K3/3405 , H05K2201/1034 , H05K2201/10924 , Y10T29/49121 , Y10T29/49126 , Y10T29/4913 , Y10T29/49133 , Y10T29/49165 , H01L2924/00014 , H01L2924/00
Abstract: The method of the present invention includes a first step of preparing a substrate in which a plurality of circuit boards are integrally connected to one another, each of the circuit boards having conductive patterns which include pads formed on a surface of the circuit board; a second step of electrically connecting circuit elements to the respective conductive patterns on each of the circuit boards; a third step of positioning ends of leads above the respective pads by superposing a lead frame including the plurality of leads on the substrate, and fixing the leads to the pads; and a fourth step of separating the circuit boards from the substrate in a state where the leads are fixed to the respective pads on each of the circuit boards, and thus separating the leads from the lead frame.
Abstract translation: 本发明的方法包括：制备其中多个电路板彼此一体地连接的基板的第一步骤，每个电路板具有包括形成在电路板的表面上的焊盘的导电图案; 将电路元件电连接到每个电路板上的各个导电图案的第二步骤; 第三步骤，通过将包括所述多个引线的引线框叠置在所述基板上，并将所述引线固定到所述焊盘，来将引线的端部定位在相应的焊盘之上; 以及在将引线固定到每个电路板上的各个焊盘的状态下将电路板与基板分离的第四步骤，从而将引线与引线框架分离。
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公开(公告)号：US07466024B2
公开(公告)日：2008-12-16
申请号：US11580904
申请日：2006-10-16
Applicant: Fujio Ito , Hiromichi Suzuki , Akihiko Kameoka , Noriaki Sakamoto
Inventor： Fujio Ito , Hiromichi Suzuki , Akihiko Kameoka , Noriaki Sakamoto
IPC: H01L23/495
CPC classification number: H01L24/85 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/06153 , H01L2224/32245 , H01L2224/45144 , H01L2224/4809 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/4912 , H01L2224/49171 , H01L2224/49175 , H01L2224/4943 , H01L2224/73265 , H01L2224/78743 , H01L2224/85148 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01055 , H01L2924/01079 , H01L2924/01082 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19043 , H01L2924/3011 , H01L2224/78 , H01L2924/00 , H01L2924/00012
Abstract: A semiconductor device comprises a microcomputer chip, an SDRAM which is disposed alongside the microcomputer chip and is thinner than the microcomputer chip, a tub, a plurality of inner leads and outer leads, first wires that connect pads of the microcomputer chip and pads of the SDRAM, and second wires which connect the pads of the microcomputer chip and the inner leads and which are disposed so as to bridge over the SDRAM and are formed with loops at positions higher than loops of the first wires. An interface circuit for a memory bus is connected only between the chips, without connecting to external terminals, and is closed within a package. Therefore, pins can be utilized for other functions correspondingly and a multi-pin configuration can be achieved. Further, the cost of an SIP (semiconductor device) can be reduced owing to the adoption of a frame type.
Abstract translation: 半导体器件包括微计算机芯片，与微计算机芯片一起设置并且比微计算机芯片薄的SDRAM，多个内引线和外引线，连接微计算机芯片的焊盘和第二引线的第一引线 SDRAM和第二线，其连接微型计算机芯片的焊盘和内部引线，并布置成跨越SDRAM并且在高于第一线的环的位置处形成有环。 用于存储器总线的接口电路仅在芯片之间连接，而不连接到外部端子，并且在封装内封闭。 因此，可以相应地使用引脚用于其他功能，并且可以实现多引脚配置。 此外，由于采用帧类型，可以降低SIP（半导体器件）的成本。
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