利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

51 条记录 (耗时 0.019 秒)

    Stacked semiconductor package
    3.
    发明授权
    Stacked semiconductor package 有权

    公开(公告)号：US11508685B2

    公开(公告)日：2022-11-22

    申请号：US16992895

    申请日：2020-08-13

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Jihwan Suh ,  Un-Byoung Kang ,  Taehun Kim ,  Hyuekjae Lee ,  Jihwan Hwang ,  Sang Cheon Park

    IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18

    摘要： A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

    Semiconductor package having dummy pads and method of manufacturing semiconductor package having dummy pads
    4.
    发明授权
    Semiconductor package having dummy pads and method of manufacturing semiconductor package having dummy pads 有权

    公开(公告)号：US11282792B2

    公开(公告)日：2022-03-22

    申请号：US16805890

    申请日：2020-03-02

    申请人： Samsung Electronics Co., Ltd.

    发明人： Young Kun Jee ,  Hae-Jung Yu ,  Sangwon Kim ,  Un-Byoung Kang ,  Jongho Lee ,  Dae-Woo Kim ,  Wonjae Lee

    IPC分类号： H01L23/538 ,  H01L25/18 ,  H01L23/498

    摘要： A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

    Semiconductor package with dummy pattern not electrically connected to circuit pattern
    9.
    发明授权
    Semiconductor package with dummy pattern not electrically connected to circuit pattern 有权

    公开(公告)号：US11658131B2

    公开(公告)日：2023-05-23

    申请号：US17168337

    申请日：2021-02-05

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jin-Woo Park ,  Un-Byoung Kang ,  Jong Ho Lee

    IPC分类号： H01L23/14 ,  H01L23/00 ,  H01L23/498

    CPC分类号： H01L23/562 ,  H01L23/14 ,  H01L23/49816 ,  H01L24/14

    摘要： A semiconductor package includes a first substrate including a circuit pattern and a dummy pattern on an upper face of the first substrate, a solder ball, a second substrate on the first substrate, and an underfill material layer between the first and second substrates. The underfill material layer wraps around the solder ball. The dummy pattern is not electrically connected to the circuit pattern. The first substrate includes a solder resist layer on the circuit pattern and the dummy pattern. The solder resist layer includes a first opening for exposing at least a part of the circuit pattern. The solder ball is in the first opening and electrically insulated from the dummy pattern by the solder resist layer. The second substrate is electrically connected to the first substrate by the solder ball. The second substrate is electrically insulated from the dummy pattern by the solder resist layer.

    Semiconductor packages including stacked substrates and penetration electrodes
    10.
    发明授权
    Semiconductor packages including stacked substrates and penetration electrodes 有权

    公开(公告)号：US11222873B2

    公开(公告)日：2022-01-11

    申请号：US16936882

    申请日：2020-07-23

    申请人： Samsung Electronics Co., Ltd.

    发明人： Joonho Jun ,  Un-Byoung Kang ,  Sunkyoung Seo ,  Jongho Lee ,  Young Kun Jee

    IPC分类号： H01L25/065 ,  H01L23/00

    摘要： A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.