-
公开(公告)号：US12094847B2
公开(公告)日：2024-09-17
申请号：US17329980
申请日：2021-05-25
发明人： Seyeong Seok , Un-Byoung Kang , Chungsun Lee
IPC分类号： H01L23/498 , H01L21/56 , H01L23/00 , H01L23/31 , H01L25/00 , H01L25/065 , H01L25/10 , H01L25/18
CPC分类号： H01L24/16 , H01L21/561 , H01L21/563 , H01L21/568 , H01L23/3121 , H01L23/49822 , H01L23/49838 , H01L24/13 , H01L24/17 , H01L24/73 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L25/18 , H01L2224/13005 , H01L2224/13024 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/73104 , H01L2224/73259 , H01L2224/73267 , H01L2224/95001 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/1035 , H01L2924/1431 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/1443
摘要： A semiconductor package may include: a first redistribution substrate; a first die above the first redistribution substrate; a second redistribution substrate on the first die; a first bump formed on the first die, and connecting the first die to the second redistribution substrate; a first molding portion enclosing the first die and surrounding the first bump; and an outer terminal on a bottom surface of the first redistribution substrate, wherein the second redistribution substrate comprises an insulating pattern and a conductive pattern in the insulating pattern to be in contact with the first bump, and wherein, at an interface of the second redistribution substrate and the first bump, the conductive pattern of the second redistribution substrate and the first bump are formed of the same material to form a single body or structure.
-
公开(公告)号：US11664312B2
公开(公告)日：2023-05-30
申请号：US17147661
申请日：2021-01-13
发明人： Ju-Il Choi , Gyuho Kang , Seong-Hoon Bae , Dongjoon Oh , Chungsun Lee , Hyunsu Hwang
IPC分类号： H01L23/532 , H01L23/00 , H01L23/48 , H01L23/522
CPC分类号： H01L23/53238 , H01L23/481 , H01L23/5226 , H01L23/5329 , H01L24/05 , H01L24/08 , H01L24/16 , H01L2224/05647 , H01L2224/08145 , H01L2224/16227
摘要： A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.
-
公开(公告)号：US09023716B2
公开(公告)日：2015-05-05
申请号：US14147718
申请日：2014-01-06
发明人： Chungsun Lee , Jung-Seok Ahn , Kwang-chul Choi , Un-Byoung Kang , Jung-Hwan Kim , Joonsik Sohn , Jeon Il Lee
IPC分类号： H01L21/58 , H01L21/304 , H01L21/683
CPC分类号： H01L21/6835 , B32B37/1284 , B32B37/18 , B32B37/24 , B32B37/26 , B32B38/04 , B32B38/10 , B32B38/162 , B32B2037/268 , B32B2315/08 , B32B2457/14 , H01L21/02057 , H01L21/02126 , H01L21/304 , H01L21/6836 , H01L21/76898 , H01L24/03 , H01L24/14 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68363 , H01L2221/68372 , H01L2221/68381 , H01L2224/0401 , H01L2224/05025 , H01L2224/13023 , H01L2924/12042 , H01L2924/181 , Y10S438/977 , H01L2924/00
摘要： A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.
摘要翻译： 一种处理衬底的方法包括：在衬底和载体之间提供接合层，以将衬底粘合到载体上，在衬底由载体支撑的同时处理衬底，以及去除结合层以使衬底与载体分离。 粘合层可以包括热固性剥离层和热固性胶层，其中至少一个热固性胶层设置在热固性剥离层的每一侧上。
-
公开(公告)号：US12021034B2
公开(公告)日：2024-06-25
申请号：US17198359
申请日：2021-03-11
发明人： Solji Song , Byeongchan Kim , Jumyong Park , Jinho An , Chungsun Lee , Jeonggi Jin , Juil Choi
IPC分类号： H01L23/538 , H01L23/00 , H01L25/065
CPC分类号： H01L23/5386 , H01L23/5383 , H01L24/16 , H01L25/0655 , H01L2224/16227
摘要： A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.
-
公开(公告)号：US20240203888A1
公开(公告)日：2024-06-20
申请号：US18430066
申请日：2024-02-01
发明人： Hyunsu Hwang , Junyun Kweon , Jumyong Park , Jin Ho An , Dongjoon Oh , Chungsun Lee , Ju-il Choi
IPC分类号： H01L23/538 , H01L21/48 , H01L25/065 , H01L25/10
CPC分类号： H01L23/5383 , H01L21/4857 , H01L23/5386 , H01L25/0652 , H01L25/105 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06586 , H01L2225/06589 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058
摘要： Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.
-
公开(公告)号：US20230395403A1
公开(公告)日：2023-12-07
申请号：US18134718
申请日：2023-04-14
发明人： Jinwoo Park , Myungsung Kang , Jaekyung Yoo , Unbyoung Kang , Chungsun Lee
IPC分类号： H01L21/67
CPC分类号： H01L21/67126
摘要： A molding apparatus for a semiconductor package includes a chamber including a lower mold configured to hold a substrate including a plurality of molding targets, an upper mold configured to move up and down with respect to the lower mold and define a cavity between the upper mold and the lower mold, and a port configured to provide a passage communicating with the cavity, a molding material supplier configured to supply a molding material to the port, a plunger configured to pressurize the molding material inside the port, a plunger actuator configured to apply a first pressure to the plunger such that the molding material provided in the port is supplied to the cavity, and a mold actuator configured to control actuation of the upper mold. The plunger actuator is configured to supply the molding material to the cavity by applying the first pressure to the plunger, and the mold actuator is configured to pressurize the molding material in the cavity by applying a second pressure to the upper mold. The mold apparatus further includes a controller configured to control the plunger actuator to reduce the first pressure applied to the plunger after the mold actuator begins applying the second pressure to the upper mold.
-
公开(公告)号：US09412636B2
公开(公告)日：2016-08-09
申请号：US14682231
申请日：2015-04-09
发明人： Chungsun Lee , Jung-Seok Ahn , Kwang-chul Choi , Un-Byoung Kang , Jung-Hwan Kim , Joonsik Sohn , Jeon Il Lee
IPC分类号： H01L21/58 , H01L21/683 , H01L21/304 , B32B37/12 , B32B37/18 , B32B37/24 , B32B37/26 , B32B38/04 , B32B38/10 , B32B38/16 , H01L21/02 , H01L21/768 , H01L23/00
CPC分类号： H01L21/6835 , B32B37/1284 , B32B37/18 , B32B37/24 , B32B37/26 , B32B38/04 , B32B38/10 , B32B38/162 , B32B2037/268 , B32B2315/08 , B32B2457/14 , H01L21/02057 , H01L21/02126 , H01L21/304 , H01L21/6836 , H01L21/76898 , H01L24/03 , H01L24/14 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68363 , H01L2221/68372 , H01L2221/68381 , H01L2224/0401 , H01L2224/05025 , H01L2224/13023 , H01L2924/12042 , H01L2924/181 , Y10S438/977 , H01L2924/00
摘要： A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.
-
公开(公告)号：US12009288B2
公开(公告)日：2024-06-11
申请号：US17230511
申请日：2021-04-14
发明人： Dongjoon Oh , Junyun Kweon , Jumyong Park , Jin Ho An , Chungsun Lee , Hyunsu Hwang
IPC分类号： H01L23/498 , H01L23/31 , H01L23/538 , H01L23/00 , H01L25/10
CPC分类号： H01L23/49822 , H01L23/3128 , H01L23/5386 , H01L23/5389 , H01L24/16 , H01L25/105 , H01L2224/16227
摘要： Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.
-
公开(公告)号：US11996358B2
公开(公告)日：2024-05-28
申请号：US17364558
申请日：2021-06-30
发明人： Ju-Il Choi , Jumyong Park , Jin Ho An , Dongjoon Oh , Chungsun Lee , Jeonggi Jin , Jinho Chun
IPC分类号： H01L23/498
CPC分类号： H01L23/49838 , H01L23/49822
摘要： A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.
-
公开(公告)号：US20230089399A1
公开(公告)日：2023-03-23
申请号：US17719721
申请日：2022-04-13
发明人： Solji SONG , Junyun Kweon , Jumyong Park , Dongjoon Oh , Chungsun Lee , Hyunsu Hwang
IPC分类号： H01L23/528 , H01L23/532 , H01L21/78 , H01L23/498 , H01L25/00 , H01L25/065 , H01L23/00 , H01L23/16
摘要： A semiconductor device includes a substrate, an insulating layer on a bottom surface of the substrate, a portion of a top surface of the insulating layer that faces the substrate being exposed outside a side surface of the substrate, a through via penetrating the substrate, an interconnection structure in the insulating layer, and a dummy pattern on the portion of the top surface of the insulating layer that is exposed by the substrate.
-
-
-
-
-
-
-
-
-
搜索结果
27 条记录 (耗时 0.021 秒)
