公开(公告)号：US07605020B2

公开(公告)日：2009-10-20

申请号：US11612393

申请日：2006-12-18

申请人： Su Tao ,  Shih Chang Lee

发明人： Su Tao ,  Shih Chang Lee

IPC分类号： H01L21/00

CPC分类号： H01L23/36 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method of manufacturing a semiconductor chip package includes mechanically and electrically connecting a semiconductor chip to a top surface of a main substrate, securely attaching the semiconductor chip to a recessed cavity on a bottom surface of an interconnection substrate, mechanically and electrically connecting the main substrate to the interconnection substrate, and cutting the main substrate to form a central substrate and a peripheral substrate wherein the semiconductor chip is disposed on the central substrate. The cutting step is conducted either (i) by forming a plurality of slots such that the central substrate and the peripheral substrate are partially conned to each other or (ii) by completely separating the central substrate and the peripheral substrate.

摘要翻译： 制造半导体芯片封装的方法包括将半导体芯片机械地和电连接到主基板的顶表面，将半导体芯片牢固地连接到互连基板的底表面上的凹腔中，机械地和电连接主基板 并且切割主基板以形成中心基板和外围基板，其中半导体芯片设置在中心基板上。 切割步骤（i）通过形成多个狭缝进行，使得中心基板和外围基板彼此部分连接，或者（ii）通过完全分离中心基板和外围基板。

公开(公告)号：US07102241B2

公开(公告)日：2006-09-05

申请号：US10929503

申请日：2004-08-31

申请人： Su Tao

发明人： Su Tao

IPC分类号： H01L23/29 ,  H01L23/48

CPC分类号： H01L23/492 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A leadless semiconductor package disposed on a substrate includes a chip, a plurality of leads, wherein each lead has a metal layer and a first molding compound formed on the metal layer, a second molding compound disposed on the first molding compound, and a chip paddle for carrying the chip. The leads are connected to the chip by wire bonding technique. The metal layer is exposed out of the first molding compound; and the second molding compound encapsulates the chip with the chip paddle exposed out of the second molding compound.

摘要翻译： 设置在基板上的无引线半导体封装包括芯片，多个引线，其中每个引线具有金属层和形成在金属层上的第一模塑料，设置在第一模塑料上的第二模塑料和芯片桨 用于携带芯片。 引线通过引线接合技术连接到芯片。 金属层露出第一模塑料; 并且所述第二模塑料封装所述芯片，所述芯片焊盘暴露于所述第二模塑料之外。

公开(公告)号：US07037759B2

公开(公告)日：2006-05-02

申请号：US10864408

申请日：2004-06-10

申请人： Su Tao

发明人： Su Tao

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/05124

摘要： A semiconductor package comprises a semiconductor chip, a lid, a plurality of traces, a compliant layer, a plurality of conductive pastes, and a plurality of solder pads. The semiconductor chip has an active surface, a backside, and a plurality of bonding pads disposed on the active surface. The lid covers the active surface of the semiconductor chip. The traces are disposed between the lid and the active surface of the semiconductor chip, and are electrically connected to the bonding pads. The compliant layer covers the backside of the semiconductor chip for isolating the traces. The conductive pastes are electrically connected to the traces, and the solder pads are electrically connected to the conductive pastes.

公开(公告)号：US07002257B2

公开(公告)日：2006-02-21

申请号：US10463578

申请日：2003-06-18

申请人： Su Tao ,  Kuo-Chung Yee ,  Jen-Chieh Kao

发明人： Su Tao ,  Kuo-Chung Yee ,  Jen-Chieh Kao

IPC分类号： H01L23/28

CPC分类号： H01L27/14618 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L27/14683 ,  H01L31/0203 ,  H01L31/0232 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： An optical component package includes a substrate, an optical component, a plurality of spacers, a plurality of wires, and a transparent molding compound. The optical component is disposed on the substrate, and the surface of the optical component located away from the substrate is used to receive an optical signal. The spacers are disposed between the substrate and optical component. The wires electrically connect the optical component to the substrate. The transparent molding compound encapsulates the optical component. In this case, the diameter of each of the spacers is equal to the thickness of the transparent molding compound minus the thickness of the optical component minus the distance between where the optical signal enters the transparent molding compound and where the optical signal is received by the optical component. Furthermore, this invention also discloses a packaging method for the optical component package.

摘要翻译： 光学部件封装包括基板，光学部件，多个间隔件，多根电线以及透明模塑料。 光学部件设置在基板上，并且使用远离基板的光学部件的表面来接收光信号。 间隔件设置在基板和光学部件之间。 电线将光学部件电连接到基板。 透明模塑料封装光学部件。 在这种情况下，每个间隔物的直径等于透明模塑料的厚度减去光学部件的厚度减去光信号进入透明模塑料之间的距离，并且光信号由 光学元件。 此外，本发明还公开了一种用于光学部件封装的封装方法。

公开(公告)号：US06946729B2

公开(公告)日：2005-09-20

申请号：US10417693

申请日：2003-04-17

申请人： Chun-Chi Lee ,  Su Tao

发明人： Chun-Chi Lee ,  Su Tao

IPC分类号： H01L23/31 ,  H01L23/433 ,  H01L23/34 ,  H01L23/02 ,  H01L23/48 ,  H01L23/495 ,  H05K7/20

CPC分类号： H01L24/49 ,  H01L23/3128 ,  H01L23/4334 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A wafer level package structure and a method for packaging said wafer level package structure are described. The wafer level package structure at least comprises a die, a heat slug covering said die, a carrier for supporting said heat slug and said die, a plurality of wires electrically connecting said die and said carrier, and a mould compound encapsulating said die, said carrier, said heat slug and said wires. The method comprises the steps of: (a)providing a heat slug metal with a plurality of openings; (b)mounting said heat slug metal onto a wafer to dispose said openings on corresponding bonding pads of the wafer so as to expose said bonding pads; (c)sawing said combined heat slug metal and wafer into a plurality of die units; (d)attaching said die unit onto a carrier; (e)electrically connecting a plurality of wires to said die unit and said carrier; (f)encapsulating said wired die unit and said carrier. In the present invention, the heat slug metal and wafer can be sawed into a plurality of die units at the same time to improve the defect of the complicated process of individually sawing heat slug metal and wafer and individually combining heat slug metal and wafer in the conventional method.

摘要翻译： 描述了晶片级封装结构和用于封装晶片级封装结构的方法。 晶片级封装结构至少包括一个管芯，一个覆盖所述管芯的散热片，一个用于支撑所述加热块和所述管芯的载体，多个电连接所述管芯和所述载体的电线以及封装所述管芯的模具化合物， 载体，所述热塞和所述电线。 该方法包括以下步骤：（a）提供具有多个开口的热块金属; （b）将所述加热块金属安装在晶片上以将所述开口布置在所述晶片的对应的焊盘上，以暴露所述焊盘; （c）将所述组合的热块金属和晶片锯切成多个模具单元; （d）将所述模具单元附接到载体上; （e）将多根电线电连接到所述模具单元和所述载体上; （f）封装所述有线芯片单元和所述载体。 在本发明中，可以同时将散热块金属和晶片锯成多个模具单元，以改善单独锯切热芯金属和晶片的复杂工艺的缺陷，并且将热块金属和晶片分别组合在 常规方法。

公开(公告)号：US20050189641A1

公开(公告)日：2005-09-01

申请号：US11115236

申请日：2005-04-27

申请人： Su Tao ,  Chi Chiu ,  Sung Wu

发明人： Su Tao ,  Chi Chiu ,  Sung Wu

IPC分类号： H01L21/56 ,  H01L21/58 ,  H01L23/31 ,  H01L23/66 ,  H01L25/065 ,  H01L23/02

CPC分类号： H01L23/66 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/315 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package comprises a first chip, a substrate, a middle layer, a second chip, and an encapsulant. The first chip has an active surface and a high-frequency element defining a high-frequency area on the active surface. The substrate supports the first chip and is electrically connected to the first chip. The middle layer is disposed on the first chip and has a recess corresponding to the high-frequency area. The second chip is disposed on the middle layer and electrically connected to either the first chip or the substrate. The encapsulant encapsulates the first chip, the middle layer, the second chip, and a part of the substrate.

公开(公告)号：US20050046046A1

公开(公告)日：2005-03-03

申请号：US10962564

申请日：2004-10-13

申请人： Chi-Tsung Chiu ,  Su Tao ,  Sung-Mao Wu

发明人： Chi-Tsung Chiu ,  Su Tao ,  Sung-Mao Wu

IPC分类号： H01L21/58 ,  H01L23/29 ,  H01L23/31 ,  H01L23/49 ,  H01L23/552 ,  H01L21/48 ,  H01L23/28

CPC分类号： H01L23/29 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2223/6611 ,  H01L2223/6622 ,  H01L2224/45144 ,  H01L2224/45572 ,  H01L2224/45599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/83 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/05442 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor package structure includes a substrate, a semiconductor die, a plurality of wires, and a molding compound. In this case, the semiconductor die is attached to the substrate. Each of the wires respectively has a center conductive layer, a dielectric layer, and a metal layer. Each of the center conductive layers connects the semiconductor die to the substrate. Each of the dielectric layers covers each of the center conductive layers, and the metal layers cover the dielectric layers. The molding compound encapsulates the semiconductor die and the wires. This invention also provides another semiconductor package structure, including a substrate, a semiconductor die, a plurality of wires, and a conductive molding compound. Each of the wires respectively has a center conductive layer and a dielectric layer. The conductive molding compound is made of a conductive material. Furthermore, the invention also provides a method for manufacturing the semiconductor package structure.

摘要翻译： 半导体封装结构包括衬底，半导体管芯，多根电线和模塑料。 在这种情况下，将半导体管芯附接到基板。 各导线分别具有中心导电层，电介质层和金属层。 每个中心导电层将半导体管芯连接到衬底。 每个电介质层覆盖每个中心导电层，并且金属层覆盖电介质层。 模制化合物封装半导体管芯和电线。 本发明还提供了另一种半导体封装结构，其包括基片，半导体片，多根丝和导电模塑料。 每根导线分别具有中心导电层和电介质层。 导电模塑料由导电材料制成。 此外，本发明还提供了一种用于制造半导体封装结构的方法。

公开(公告)号：US06692581B2

公开(公告)日：2004-02-17

申请号：US10248802

申请日：2003-02-20

申请人： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Ching-Fu Horng ,  Shih-Kuang Chen ,  Shyh-Ing Wu ,  Chun-Hung Lin ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

发明人： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Ching-Fu Horng ,  Shih-Kuang Chen ,  Shyh-Ing Wu ,  Chun-Hung Lin ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

IPC分类号： B23K35363

CPC分类号： H01L24/10 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/262 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K3/3484 ,  H05K2201/0266 ,  H05K2203/043 ,  H01L2924/00

摘要： A solder paste for fabricating bumps includes a flux and metallic alloy powder. The metallic alloy powder includes a plurality of low eutectic metallic alloy granules, and the size of these metallic alloy granules is 20-60 &mgr;m and the average size of the metallic granules is 35 &mgr;m to 45 &mgr;m.

摘要翻译： 用于制造凸块的焊膏包括焊剂和金属合金粉末。 金属合金粉末包含多个低共晶金属合金颗粒，这些金属合金颗粒的尺寸为20-60μm，金属颗粒的平均尺寸为35μm〜45μm。

公开(公告)号：US06664128B2

公开(公告)日：2003-12-16

申请号：US10248716

申请日：2003-02-12

申请人： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

发明人： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

IPC分类号： H01L2144

CPC分类号： C25F3/02 ,  C23F1/26 ,  H01L21/32134 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3473 ,  H05K2203/054 ,  H01L2224/13099 ,  H01L2924/00014

摘要： The present invention provides a bump fabrication process. After forming an under bump metallurgy (UBM) layer and bumps in sequence over the substrate, the under bump metallurgy layer that is not covered by the bumps is etched with an etchant. The etchant mainly comprises sulfuric acid and de-ionized water. The etchant can etch the nickel-vanadium layer of the UBM layer without damaging the bumps.

摘要翻译： 本发明提供一种凸块制造工艺。 在衬底上顺序地形成凹凸不平的冶金（UBM）层和凸块之后，用蚀刻剂蚀刻未被凸块覆盖的凸块下金属层。 蚀刻剂主要包括硫酸和去离子水。 蚀刻剂可以蚀刻UBM层的镍钒层，而不会损坏凸块。

公开(公告)号：US06461897B2

公开(公告)日：2002-10-08

申请号：US09854486

申请日：2001-05-15

申请人： Chun Hung Lin ,  Kuang-Hui Chen ,  Shyh-Wei Wang ,  Su Tao

发明人： Chun Hung Lin ,  Kuang-Hui Chen ,  Shyh-Wei Wang ,  Su Tao

IPC分类号： H01L2144

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/01087 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A multichip module comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.

摘要翻译： 多芯片模块包括至少两个半导体芯片，其中每个半导体芯片具有在其有效表面上形成并沿着其一个侧边缘设置的一排焊盘。 半导体芯片以堆叠方式安装到基板上，其中上芯片以下述方式附接到下芯片的有源表面，使得上芯片的任何部分不影响下芯片的每个键合焊盘的垂直视线 芯片以允许其引线接合。 因此，在将芯片堆叠在基板上之后，所有半导体芯片都可以同时引线接合。 这允许所有芯片的线接合在一个步骤中完成，以便增加UPH（每小时单位），从而降低制造MCM的成本。