摘要:
Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要:
Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要:
Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要:
Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要:
In a specific embodiment, the present invention provides an LCOS device. The device has a semiconductor substrate, e.g., silicon substrate. The device has a transistor formed within the semiconductor substrate. The transistor has a first node, a second node, and a row node. A first capacitor structure is coupled to the transistor. The first capacitor structure includes a first polysilicon layer coupled to the second node of the transistor. The first capacitor structure also has a first capacitor insulating layer overlying the first polysilicon layer and a second polysilicon layer overlying the insulating layer. The second polysilicon layer is coupled to a reference potential, e.g., ground. The device has a second capacitor structure coupled to the transistor. The second capacitor structure has a first metal layer coupled to the reference potential, a second capacitor insulating layer, and a second metal layer coupled to the second node of the transistor. A pixel electrode comprises the first metal layer. The pixel electrode is coupled to the second node of the transistor. A mirror surface is on the pixel electrode. The device has a light shielding layer formed from a portion of the second metal layer.
摘要:
In a specific embodiment, the present invention provides an LCOS device. The device has a semiconductor substrate, e.g., silicon substrate. The device has a transistor formed within the semiconductor substrate. The transistor has a first node, a second node, and a row node. A first capacitor structure is coupled to the transistor. The first capacitor structure includes a first polysilicon layer coupled to the second node of the transistor. The first capacitor structure also has a first capacitor insulating layer overlying the first polysilicon layer and a second polysilicon layer overlying the insulating layer. The second polysilicon layer is coupled to a reference potential, e.g., ground. The device has a second capacitor structure coupled to the transistor. The second capacitor structure has a first metal layer coupled to the reference potential, a second capacitor insulating layer, and a second metal layer coupled to the second node of the transistor. A pixel electrode comprises the first metal layer. The pixel electrode is coupled to the second node of the transistor. A mirror surface is on the pixel electrode. The device has a light shielding layer formed from a portion of the second metal layer.
摘要:
The present invention provides an LCOS device having improved bonding pad features. The device has a substrate, a transistor layer overlying the substrate and an interlayer dielectric layer overlying the transistor layer. A first conductive layer is overlying the interlayer dielectric layer and a second interlayer dielectric layer is overlying the first conductive layer. An enlarged opening for a bonding pad structure is in a first portion of the second interlayer dielectric layer. A barrier metal layer is formed within the enlarged opening to form a liner that covers exposed regions of the enlarged opening. A metal material is overlying the liner to fill the enlarged opening. A thickness of an aluminum material is overlying the metal material. The device has a bonding pad structure formed from a first portion of the thickness of the aluminum material and is coupled to the metal material in the enlarged opening.
摘要:
A liquid crystal on silicon display device (LCOS) has a semiconductor substrate comprising a surface region and a gate dielectric layer overlying the surface region. The device also has a word line formed overlying the gate dielectric layer and a first source/drain region coupled to the word line. The device has a bottom electrode structure formed overlying an interlayer dielectric. A capacitor dielectric is formed overlying the bottom electrode. A top electrode structure is formed overlying the capacitor dielectric to form a capacitor structure including the bottom electrode structure, the capacitor dielectric, and the top electrode structure. The device has a mirror surface formed overlying the top electrode structure to form a pixel electrode structure and a liquid crystal material provided overlying the mirror surface. In an embodiment, the LCOS described above is in an integrated circuit chip that also includes a DRAM device.
摘要:
A liquid crystal on silicon display device (LCOS) has a semiconductor substrate comprising a surface region and a gate dielectric layer overlying the surface region. The device also has a word line formed overlying the gate dielectric layer and a first source/drain region coupled to the word line. The device has a bottom electrode structure formed overlying an interlayer dielectric. A capacitor dielectric is formed overlying the bottom electrode. A top electrode structure is formed overlying the capacitor dielectric to form a capacitor structure including the bottom electrode structure, the capacitor dielectric, and the top electrode structure. The device has a mirror surface formed overlying the top electrode structure to form a pixel electrode structure and a liquid crystal material provided overlying the mirror surface. In an embodiment, the LCOS described above is in an integrated circuit chip that also includes a DRAM device.
摘要:
The present invention provides an LCOS device having improved bonding pad features. The device has a substrate, a transistor layer overlying the substrate and an interlayer dielectric layer overlying the transistor layer. A first conductive layer is overlying the interlayer dielectric layer and a second interlayer dielectric layer is overlying the first conductive layer. An enlarged opening for a bonding pad structure is in a first portion of the second interlayer dielectric layer. A barrier metal layer is formed within the enlarged opening to form a liner that covers exposed regions of the enlarged opening. A metal material is overlying the liner to fill the enlarged opening. A thickness of an aluminum material is overlying the metal material. The device has a bonding pad structure formed from a first portion of the thickness of the aluminum material and is coupled to the metal material in the enlarged opening.